3D NAND Virtual Process Troubleshooting And Investigation

By Brett Lowe - 18 Aug, 2022 - Comments: 0

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form of unanticipated negative interactions between upstream and downstream process modules. These barriers can create a long delay in the development cycle and increase costs. ... » read more

Hybrid Bonding Basics: What Is Hybrid Bonding?

By Jessica Albright - 18 Aug, 2022 - Comments: 2

Hybrid bonding is the key to paving an innovative future in advanced packaging. Hybrid bonding provides a solution that enables higher bandwidth and increased power and signal integrity. As the industry is looking to enhance the performance of final devices through scaling system-level interconnections, hybrid bonding provides the most promising solution with the ability to integrate several di... » read more

Fan-Out Packaging Gets Competitive

By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Equipment Suppliers Brace For GaN Market Explosion

By Adele Hars - 18 Aug, 2022 - Comments: 0

A huge GaN market is opening up, driven by consumer devices and the need for greater energy efficiency across many applications. Suppliers are ready, but to fully compete with SiC in high-voltage automotive applications will require further technological developments in power GaN (gallium nitride). Still, the 2020s mark a very high-growth phase for GaN markets. Revenues in the power GaN mark... » read more

Collaborating To Decarbonize The Semiconductor Manufacturing Value Chain

By Mousumi Bhat - 18 Aug, 2022 - Comments: 0

By Mousumi Bhat and Peter Spiller SEMICON West 2022 Hybrid gathered experts from across the semiconductor industry for the debut Sustainability Summit to talk about the sustainability of the industry’s growth. Semiconductor chips have become ubiquitous in recent years. All aspects of society have become extremely dependent on semiconductors. The post-pandemic revenue growth of semicondu... » read more

Heterogeneous IC Packaging: Optimizing Performance And Cost

By Mike Kelly - 18 Aug, 2022 - Comments: 0

Leading integrated circuit (IC) foundries are already shipping 7-nm and 5-nm wafers and 3-nm product qualifications are ongoing. Wafer costs continue to soar as high transistor density requires ever more expensive processes to fabricate them. Even if defect densities can remain relatively flat as new nodes emerge, the cost per unit area of silicon increases nonlinearly. These economics have pla... » read more

Heterogeneous Integration Device Assembly: Key To Enabling Additional Innovations

By Dick Otte - 18 Aug, 2022 - Comments: 0

Heterogeneous integration (HI) improves device functionality by expanding the types of parts and physical configurations combined with silicon chips. Different parts add new functions – with minimal additional volume – thus increasing overall functionality per unit volume. By comparison, classic methods employed to build electronic products, e.g., circuit boards or metal boxes, increase pro... » read more

A Novel Photosensitive Permanent Bonding Material Designed For Polymer/Metal Hybrid Bonding Applications

By Brewer Science - 18 Aug, 2022 - Comments: 0

Wafer-level hybrid bonding techniques, which provide simultaneous bonding between metal-metal and dielectric-dielectric layers, have attracted more attention in recent years for fabricating 3D integrated circuits with high bandwidth and high interconnect density. However, there are some issues for conventional hybrid bonding using silicon oxide as the dielectric, such as the high stress and low... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 12 Aug, 2022 - Comments: 0

Government funding President Biden signed the CHIPS and Science Act into law on Tuesday, saying “America is back and leading the way.” That same day Micron touted a $40 billion investment through to 2030, which it expects will create 40,000 American jobs. “This legislation will enable Micron to grow domestic production of memory from less than 2% to up to 10% of the global market in t... » read more

Week In Review, Manufacturing, Test

By Karen Heyman - 05 Aug, 2022 - Comments: 1

Post-CHIPS Act Micron is discussing a potential new fab that could employ thousands of workers, following the passage of the Chips and Science Act. Idaho is hoping it will be built near its headquarters facilities in Boise, but Micron hasn’t committed publicly. Rob Beard, senior vice president, general counsel and corporate secretary at Micron, told the Idaho Statesman the company is consi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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