SVT: Six Stacked Vertical Transistors

By Coventor - 17 Mar, 2021 - Comments: 0

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell ... » read more

Defect Mitigation And Characterization In Silicon Hardmask Materials

By Brewer Science - 17 Mar, 2021 - Comments: 0

From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Chip Board Interaction Analysis Of 22nm FD-SOI Technology In WLP

By Amkor - 17 Mar, 2021 - Comments: 0

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applicatio... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

By eBeam Initiative - 17 Mar, 2021 - Comments: 0

The Survey: 2021 Deep Learning Applications List by eBeam Initiative members is a list of current deep learning efforts that are being used in photomask to wafer semiconductor manufacturing. Examples come from ASML, D2S, Fraunhofer IPMS, Hitachi High-Tech Corporation, imec, Siemens Industries Software, Inc., Siemens EDA, STMicroelectronics, and TASMIT. Published by the eBeam Initiative Membe... » read more

Manufacturing Bits: March 16

By Mark LaPedus - 16 Mar, 2021 - Comments: 0

Tripping up neural networks For years, Russia has been an active area in R&D. In one example, Russia's Skolkovo Institute of Science and Technology (Skoltech) has demonstrated how certain patterns can cause neural networks to make mistakes in recognizing images. Leveraging the theory behind this research, Skoltech can design defenses for pattern recognition systems that are vulnerable t... » read more

The Benefits Of Curvilinear Shapes On Photomasks

By Jan Willis - 15 Mar, 2021 - Comments: 0

Do you have four minutes to hear why companies like Micron Technology think that curvilinear shapes on photomasks are an advantage? In a short video, Ezequiel Russell, Senior Director of Mask Technology at Micron Technology shows how curvilinear shapes can increase process windows for advanced memory as shown in figure 1. The video was part of a longer panel discussion with industry experts at ... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 12 Mar, 2021 - Comments: 0

Government policy For the last four years, the U.S. and China have been embroiled in a trade war, especially on the technology front. The U.S. has implemented a number of export control measures and tariffs in the arena. But there might be a thawing in the tense relationship between the two superpowers. “Reports surfaced Thursday indicating the China Semiconductor Industry Association (CSIA)... » read more

Changing The Rules For Chip Scaling

By Ed Sperling - 10 Mar, 2021 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

Manufacturing Bits: March 8

By Mark LaPedus - 08 Mar, 2021 - Comments: 0

Two-beam EUV lithography At the recent SPIE Advanced Lithography conference, Nikon gave a presentation on a two-beam extreme ultraviolet (EUV) lithography technology. Still in the conceptual phase, Nikon’s so-called EUV Projection Optical Wafer Exposure Ruling Machine, or EUV Power Machine, is designed for the 1nm node or so. The proposed system has a minimum resolution of 10nm for lines ... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 05 Mar, 2021 - Comments: 0

Government policy The National Security Commission on Artificial Intelligence (NSCAI) this week submitted its final report to Congress and the President. The goal is to develop a national strategy to maintain America’s AI advantages related to national security. As part of the long and complex report, the NSCAI came to a sobering conclusion: “The U.S. government is not prepared to defend t... » read more

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Knowledge Centers
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category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

SVT: Six Stacked Vertical Transistors

Defect Mitigation And Characterization In Silicon Hardmask Materials

Chip Board Interaction Analysis Of 22nm FD-SOI Technology In WLP

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

Manufacturing Bits: March 16

The Benefits Of Curvilinear Shapes On Photomasks

Week In Review: Manufacturing, Test

Changing The Rules For Chip Scaling

Manufacturing Bits: March 8

Week In Review: Manufacturing, Test