Week In Review: Manufacturing, Test


Intel aims to quadruple capacity for its most advanced chip packaging services by 2025, including with a new facility in Malaysia, per Nikkei Asia. Huawei is building a collection of secret semiconductor fabrication facilities across China to let the company skirt U.S. sanctions, SIA warned in a presentation seen by Bloomberg. It’s acquired at least two existing plants and is building at l... » read more

Blog Review: Aug. 23


Siemens' Stephen Chavez discusses best practices when it comes to thermal analysis for PCB design, including component placement and close collaboration between mechanical and electrical engineering disciplines. Synopsys' Gary Ruggles, Richard Solomon, and Varun Agrawal introduce the Compute Express Link (CXL) specification and how it could help improve latency through computational offloadi... » read more

Week In Review: Semiconductor Manufacturing, Test


Intel dropped out of a $5.4 billion deal to purchase Tower Semiconductor in Israel. Intel cited the inability to obtain regulatory approval in a timely manner as the reason for ending the deal signed in February. Intel will pay a $353 million termination fee to Tower. The silicon wafer supply has moved back into positive territory for 2023 thanks to a 7% decline in wafer shipments combined w... » read more

Week In Review: Automotive, Security and Pervasive Computing


The AAA Foundation for Traffic Safety estimates that between 2021 and 2050, ADAS technologies currently available to U.S. will prevent "approximately 37 million crashes, 14 million injuries, and nearly 250,000 deaths, which would represent 16% of crashes and injuries, and 22% of deaths that would otherwise occur on U.S. roads without these technologies," according to a new report. Governmen... » read more

Week In Review: Design, Low Power


Synopsys’ board of directors appointed Sassine Ghazi as president and chief executive officer effective on Jan. 1, 2024. Ghazi, who is currently the COO, will succeed Aart de Geus, co-founder, chair, and CEO of Synopsys, who will then become the executive chair of board of directors. IBM Research introduced  an energy-efficient mixed-signal analog AI chip for DNN inferencing and demonstra... » read more

Blog Review: Aug. 16


Synopsys' Johannes Stahl and Tim Kogel suggest that multi-die systems require a new approach at the architecture planning phase and why chip designers can’t ignore physical effects such as layout, power, temperature, or IR-drop. Siemens' Rich Edelman argues for using the waveform window in a GUI rather than $display when debugging UVM. Cadence's Paul Scannell stresses the need for diver... » read more

Week In Review: Manufacturing, Test


TSMC, Bosch, Infineon, and NXP will jointly invest in the European Semiconductor Manufacturing Co. (ESMC), in Dresden, Germany, to provide advanced semiconductor manufacturing services. ESMC marks a significant step toward construction of a 300mm fab, which is expected to have a monthly production capacity of 40,000 300mm (12-inch) wafers on TSMC’s 28/22nm planar CMOS and 16/12nm finFET proce... » read more

Week In Review: Auto, Security, Pervasive Computing


Intel issued an advisory of a potential security vulnerability in some of its processors. The company recommends updating to the latest firmware version. NVIDIA unveiled its GH200 Grace Hopper platform, based on 144 Arm Neoverse cores and 282GB of HBM3e memory. Meanwhile, Chinese internet companies including Baidu, ByteDance, Tencent, and Alibaba ordered about $5 billion worth of A800 proces... » read more

Week In Review: Design, Low Power


U.S. President Joe Biden issued an executive order to restrict U.S. investment in Chinese companies, targeting semiconductors and microelectronics, quantum information technologies, and artificial intelligence systems with military or intelligence applications. Specific technologies within these groups will be defined later. Some will only require investors to notify the Department of the Tre... » read more

Blog Review: Aug. 9


Synopsys' John Swanson and Manmeet Walia note that designing for 224G Ethernet will entail some unique considerations, as design margins will be extremely tight, making it mission-critical to optimize individual analog blocks to reduce impairments. Cadence's Rick Sanborn finds that knowing how best to debug common partitioning-related issues and implicitly control them using common features ... » read more

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