Problems In Testing AI Chips


As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging


The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

AI For Test: The New Frontier


Dr. Ming Zhang, PDF Solutions vice president of Fabless Solutions, delivered the keynote at the TestConX 2025 conference in March. As he began his presentation, Ming borrowed the “learn, explore and share” line from Ira Feldman, the organizer of the conference, to set the tone of his talk. He promised to share what he and PDF Solutions learned and what’s useful and what’s not useful as ... » read more

Better ATPG To Minimize Chip Test Time And Cost


As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

Shifting Left With DFT To Optimize Productivity, Testability, And Time-To-Market


This paper discusses one of the Siemens EDA shift-left strategies in the RTL-to-signoff flow: shift-left design-for-test (DFT). Tessent RTL Pro software automates the analysis and insertion of Tessent VersaPoint test point technology, LBIST-OST test points, dedicated scan wrapper cells and x-bounding logic as behavioral code at the RTL level. Tessent RTL Pro builds on Tessent’s market-leading... » read more

Identifying Sources Of Silent Data Corruption


Silent data errors are raising concerns in large data centers, where they can propagate through systems and wreak havoc on long-duration programs like AI training runs. SDEs, also called silent data corruption, are technically rare. But with many thousands of servers, which contain millions of processors running at high utilization rates, these damaging events become common in large fleets. ... » read more

IoT Security By Design


After years of anticipation and steady uptake, the Internet of Things (IoT) seems poised to cross over into mainstream business use. The percentage of businesses utilizing IoT technologies has risen from 13% in 2014 to approximately 25% today. Global projections indicate that the number of IoT-connected devices is expected to reach 43 billion by 2030, nearly tripling from the figures in 2018. O... » read more

Coaxial Test Sockets Are In The Critical Path Of Advanced AI/CPU Products


Advanced AI/CPU processors demand extreme high frequency and power performance from SLT and ATE test sockets. These sockets are in the critical path at the end of a very costly silicon fabrication and advanced packaging manufacturing process. Yield loss at this point in the process is catastrophic to the bottom line. We at Modus Test, working in conjunction with our customers, have seen first-h... » read more

E-Beam Inspection Proves Essential For Advanced Nodes


Electron-beam inspection is proving to be indispensable for finding critical defects at sub-5nm dimensions. The challenge now is how to speed up the process to make it economically palatable to fabs. E-beam inspection's notorious sensitivity-throughput tradeoff has made comprehensive defect coverage with e-beam at these advanced nodes especially problematic. For Intel’s 18A logic node (~1.... » read more

Chip Complexity Drives Innovation In Automated Test Equipment


Innovations in semiconductor technology—such as advancements in AI high-performance computing (HPC), Angstrom-scale silicon process nodes, silicon photonics, and automotive xEV wideband gap power transistor applications—require automated test equipment (ATE) to evolve at an unprecedented rate. As chip complexity grows, the challenges in design, manufacturing, and test multiply. It is a comp... » read more

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