category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Innovations Driving The Advanced Packaging Roadmap: Part One
By Keith Best - 14 Jan, 2025 - Comments: 0

Advanced IC substrates (AICS) have been marching toward the 2µm line/space (L/S) redistribution layer (RDL) technology node for some time (figure 1). However, many questions remain about the ability of organic substrates to meet the line/space requirements of the next generation of advanced packages (AP), those below 2µm L/S and perhaps to 1.5µm L/S. Simply put: are organic substrates up to ... » read more

Using Test And Metrology Data For Dynamic Process Control
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Advanced packaging is transforming semiconductor manufacturing into a multi-dimensional challenge, blending 2D front-end wafer fabrication with 2.5D/3D assemblies, high-frequency device characterization, and complex yield optimization strategies. These combinations are essential to improving performance and functionality, but they create some thorny issues for which there are no easy fixes. ... » read more

Semiconductor Manufacturing’s Transformational Challenges
By John Kibarian - 14 Jan, 2025 - Comments: 0

Semiconductor manufacturing is going through massive transformational challenges driven by strong demand for advanced computing, fueled by AI, cloud, the electrification of the economy, and the need for compute power in data centers to support these applications. With the slowdown of Moore’s Law, more compute power will not be achieved by just increasing transistor density. Not only is Moo... » read more

Cut Defects, Not Yield
By proteanTecs - 14 Jan, 2025 - Comments: 0

Many chipmakers face a difficult trade-off — improve quality without affecting yield. Traditional testing methods fail to navigate this challenge due to their limited visibility below the pass/fail limits, discarding perfectly good chips or letting small defects slip through to the field. The challenge is clear: manufacturers must achieve both quality and yield goals without sacrificing one f... » read more

Screening For Known Good Interposers
By Anne Meixner - 14 Jan, 2025 - Comments: 0

Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package. Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus... » read more

Industry Standards For Chiplets And Their Role In Test
By Jeorge Hurtarte - 14 Jan, 2025 - Comments: 0

As the semiconductor industry increasingly moves to chiplets, 2.5D/3D packaging, and heterogeneous integration, there are significant new challenges for test. Leaders like Teradyne have the technologies necessary to respond and innovate, but to keep the industry running smoothly, we need effective collaboration, and that demands standardization. Source: Arizona State University There ... » read more

Expanding The Horizon Of System Monitoring With The Arm SMCF
By Ziv Paz - 14 Jan, 2025 - Comments: 0

In an era where system complexity is scaling rapidly, real-time monitoring and predictive analytics play a pivotal role in maintaining lifetime performance and reliability. At proteanTecs, we are committed to enabling advanced diagnostics, predictive maintenance, and on-chip actionable visibility for today’s mission-critical systems, across high-performance industries. Our in-chip monitori... » read more

Experiences Estimating Test Quality And Test Escape Rates
By Ken Butler - 14 Jan, 2025 - Comments: 0

When discussing product quality in integrated circuits (ICs), two key aspects are essential: time zero defects and reliability. These concepts help distinguish between issues that appear immediately after manufacturing and those that occur over time. Understanding these distinctions is critical for ensuring that products meet the quality demands of their respective markets, particularly in h... » read more

Streaming Scan Network
By Siemens EDA - 14 Jan, 2025 - Comments: 0

Tessent Streaming Scan Network (SSN) is a system for packetized delivery of scan test patterns. It enables simultaneous testing of any number of cores with few chip-level pins, and reduces test time and test data volume. With SSN, DFT engineers have a true SoC DFT solution without compromises between implementation effort and manufacturing test cost. Challenges with DFT for complex SoCs The... » read more

No-Compromise Packetized Test Improves DFT Efforts
By Peter Orlando - 14 Jan, 2025 - Comments: 0

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these trade-offs has been to use hierarchical DFT methods in a divide-and-conquer approach. In hierarchical DFT efforts, all implementation, including pattern generation and verification, is done at the cor... » read more

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