category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Reducing Chip Test Costs With AI-Based Pattern Optimization
By Rahul Singhal - 31 Jul, 2023 - Comments: 0

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested. The slower the test throughput, the more automatic test equipment (ATE) is needed to meet production throughput demands. This is a huge issue for chip producers, since high pin counts, blazingly ... » read more

Addressing Copper Clad Laminate Processing Distortion Using Overlay Corrections
By Keith Best - 11 Jul, 2023 - Comments: 0

All great voyages must come to an end. Such is the case with our series on the challenges facing the manufacturing of advanced IC substrates (AICS), the glue holding the heterogeneous integration ship together. In our first blog, we examined how cumulative overlay drift from individual redistribution layers could significantly increase overall trace length, resulting in higher interconnect res... » read more

Mission-Critical Devices Drive System-Level Test Expansion
By Laura Peters - 11 Jul, 2023 - Comments: 0

System-level testing is becoming essential for testing complex and increasingly heterogeneous chips, driven by rising demand for reliable parts in safety- and mission-critical applications. More and more chip manufacturers are jumping on the SLT bandwagon for high-volume manufacturing (HVM) of these devices. Unlike ATE and packaged device testing, SLT mimics actual semiconductor system opera... » read more

How Software Can Help Redefine Semiconductor Validation
By Jake Azbell - 11 Jul, 2023 - Comments: 0

The rate of technological advancement is increasing faster than ever before. Although the demands for meeting aggressive time-to-market requirements and innovating at warp speed are not new, they are continuing to accelerate. To cut costs without compromising product quality, engineers are now expected to test new designs more rapidly at various stages of development. Even though many organizat... » read more

Governments Begin To Shape Metrology Directions
By Gregory Haley - 11 Jul, 2023 - Comments: 0

Disruptions to the global semiconductor supply chain caused by the COVID-19 pandemic had a severe impact in nearly every sector of the worldwide economy, and especially the worldwide semiconductor market. Due to a shortage of chips, the global auto industry alone suffered a $210 billion loss in 2021, accompanied by a 7.7 million unit production drop, according to AlixPartners, a global consulti... » read more

Ditch The Glitch
By Ramsay Allen - 11 Jul, 2023 - Comments: 0

To support the ever-growing performance demands of cutting-edge applications like automotive and hyperscaler, SoC complexity continues to increase. The emergence of multi-die technology has also compounded this complexity. To keep up with these demands, design-for-test (DFT) logic must also evolve to ensure greater levels of test robustness and silicon health. The “Shift left” concept which... » read more

Design Considerations For Ultra-High Current Power Delivery Networks
By Quaid Joher Furniturewala - 11 Jul, 2023 - Comments: 0

This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ. A power-delivery network (PDN), also called a power-distribution network, is a localized network that delivers power from voltage-regulator modules (VRMs) throughout a load board to the package’s chip pads or wafer’s die pads. The PDN includes the VRM itself, all bulk and localized capacitance, board vi... » read more

The Future Of Chiplet Reliability
By Nir Sever - 11 Jul, 2023 - Comments: 0

Chipmakers are increasingly turning to advanced packaging to overcome the reticle size limit of silicon manufacturing without increasing transistor density. This method also allows hybrid devices with dies in different process nodes while improving yield, which decreases exponentially with size. However, 2.5D/3D designs introduce a fair share of new challenges, one of the most significant be... » read more

Pinpointing Timing Delays in Complex SoCs
By Anne Meixner - 11 Jul, 2023 - Comments: 0

Telemetry circuits are becoming a necessity in complex heterogeneous chips and packages to show how these devices are behaving post-production, but fusing together relevant data to identify the sources of problems adds its own set of challenges. In the past, engineering teams could build margin into chips to offset any type of variation. But at advanced nodes and in advanced packages, tolera... » read more

Striking A Balance In Acoustic Inspection
By Ed Sperling - 12 Jun, 2023 - Comments: 0

Sound energy is a quick way to to spot voids, delamination, cracks, and other possible defects that are accessible from outside the chip or package, as well as some defects that are inside of chips. But acoustic inspection also is highly sensitive to different materials with different polarities, which can change the reflection of sound waves. Bill Zuckerman, product marketing manager at Nordso... » read more

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