Adding Differentiating Value And Reducing IP Integration Time for Your SoC


In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures


This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Packetized Scan Test


Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

Next Steps For Improving Yield


Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)


By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

Legacy Tools, New Tricks: Optical 3D Inspection


Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

How To Improve Yield Ramp For New Designs And Technology Nodes


The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification using test chips, scan chain failures account for most of the chip failures. Diagnosing those scan chain defects is a powerful way to uncover new and systematic defects. The chip maker’s goal is ... » read more

Automotive Applications Demand Silicon Lifecycle Management


Every electrical engineer learns early in university studies that automobiles are a highly demanding environment for electronics. Temperature and humidity extremes, noise and vibration, electrical interference, exposure to alpha particles, and other factors all make it hard to design and manufacture chips that will operate properly under all conditions. These challenges are exacerbated as chips... » read more

Characterization Of HEMT Vias


The Zeta-Series optical profilers provide accurate measurement and automated analysis of high aspect ratio structures such as HEMT vias using non-destructive and high throughput metrology techniques.  Introduction Wide bandgap semiconductor materials are extremely attractive for use in power electronics, due to their performance capability at high temperature, power and frequency. Among wide... » read more

Bump Height Uniformity And 3D Sensing


Achieving 3D sensing for semiconductor bump height uniformity is essential before adding photoresist. But there are challenges in using traditional methods for measuring uniformity after copper plating, which requires a combination of 3D fringe projection technology and NanoResolution inspection and metrology. Here’s what we’ve learned in a bump height uniformity case study: » read more

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