category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Adopting Predictive Maintenance On Fab Tools
By Anne Meixner - 06 Dec, 2022 - Comments: 0

Predictive maintenance, based on more and better sensor data from semiconductor manufacturing equipment, can reduce downtime in the fab and ultimately cut costs compared with regularly scheduled maintenance. But implementing this approach is non-trivial, and it can be disruptive to well-honed processes and flows. Not performing maintenance quickly enough can result in damage to wafers or the... » read more

Metrology Sampling Plans Are Key For Device Analytics And Traceability
By Mike McIntyre - 06 Dec, 2022 - Comments: 0

A mother steps on the brakes, bringing her car to a stop as she drops her kids off for dance lessons. At the time, she doesn't notice anything wrong, but when she takes her car in for its regular service appointment, the mechanic conducts a diagnostic check and discovers that the primary brake system on the car had failed because of a faulty braking controller without anyone realizing it. Fortu... » read more

High Voltage Testing Races Ahead
By Karen Heyman - 06 Dec, 2022 - Comments: 1

Voltage requirements are increasing, especially for the EV market. Even devices that might be considered relatively low voltage, such as display drivers, are now pushing past established baselines. While working with high voltages is nothing new — many engineers can recall yellow caution tape in their workplaces — the sheer number and variety of new requirements have made testing at high... » read more

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Testability Analysis Based On Ever-Evolving Technology
By Pawini Mahajan - 06 Dec, 2022 - Comments: 0

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Ensuring Your Semiconductor Test Equipment Is Protected From Rising Cybersecurity Threats
By Eli Roth - 06 Dec, 2022 - Comments: 0

Cybersecurity threats pose risks to your business every day and can attack every aspect of your operation, and these threats are only increasing. According to IBM Security’s Cost of a Data Breach Report, in 2021, the average total cost of a data breach increased by nearly 10% year over year, from $3.86M to $4.24M – the largest single year cost increase in the last seven years. Sourc... » read more

Adding Differentiating Value And Reducing IP Integration Time for Your SoC
By Synopsys - 06 Dec, 2022 - Comments: 0

In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures
By Zhenhua Chen - 06 Dec, 2022 - Comments: 0

This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Packetized Scan Test
By Siemens EDA - 06 Dec, 2022 - Comments: 0

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping cores for concurrent testing is selected programmatically, not hard-wired. This concept dramatically reduces the DFT planning and implementation effort. The Siemens solution for packetized deli... » read more

Next Steps For Improving Yield
By Laura Peters - 08 Nov, 2022 - Comments: 0

Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

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