category: Special Reports

category: IoT, Security & Automotive

Hybrid Bonding Moves Into The Fast Lane
By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Keeping IC Packages Cool
By Laura Peters and Karen Heyman - 07 Jun, 2022 - Comments: 0

Placing multiple chips into a package side-by-side can alleviate thermal issues, but as companies dive further into die stacking and denser packaging to boost performance and reduce power, they are wrestling with a whole new set of heat-related issues. The shift to advanced packaging enables chipmakers to meet demands for increasing bandwidth, clock speeds, and power density for high perform... » read more

Chip Substitutions Raising Security Concerns
By Ed Sperling - 02 Jun, 2022 - Comments: 0

Substituting chips is becoming more common in the electronics industry as shortages drag on, allowing systems vendors to continue selling everything from cars to manufacturing equipment and printer cartridges without waiting for a commoditized part. But substitutions aren't always an even swap, and they increase security risks in ways that may take years to show up or fully understand. So fa... » read more

How To Optimize A Processor
By Brian Bailey - 26 May, 2022 - Comments: 0

Optimizing any system is a multi-layered problem, but when it involves a processor there are at least three levels to consider. Architects must be capable of thinking across these boundaries because the role of each of the layers must be both understood and balanced. The first level of potential optimization is at the system level. For example, how does data come in and out of the processing... » read more

Big Changes In Embedded Software
By Ann Mutschler - 28 Apr, 2022 - Comments: 0

Every good hardware or software design starts with a structured approach throughout the design cycle, but as chip architectures and applications begin focusing on specific domains and include some version of AI, that structure is becoming more difficult to define. Embedded software, which in the past was written for very narrow functions with a minimal footprint, is increasingly getting blended... » read more

Paving The Way To Chiplets
By Mark LaPedus - 25 Apr, 2022 - Comments: 2

The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

Electric Planes Taking Off
By Susan Rambo - 07 Apr, 2022 - Comments: 0

As the aeronautics industry and aviation startups design and test zero-emissions aircraft, they are solving problems beyond just adapting to fuel sources that cut greenhouse gas emissions. Problems of weight, noise, redundancy, refueling, cost, and turnaround time are being tackled one airline seat at time. Powerful tools can help aircraft designers look at the aircraft system as a whole, fe... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips
By Mark LaPedus - 21 Mar, 2022 - Comments: 0

Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Fundamental Shifts In IC Manufacturing Processes
By Ed Sperling - 14 Mar, 2022 - Comments: 2

High chip value and 3D packaging are changing where and how tests are performed, tightening design-for-reliability and accelerating the shift of tools from lab to fab. Heterogeneous integration and more domain-specific designs are causing a string of disruptions for chip manufacturers, up-ending proven fab processes and methodologies, extending the time it takes to manufacture a chip, and ul... » read more

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