category: System-Level Design

category: IoT, Security & Automotive

Blog Review: July 2
By Jesse Allen - 02 Jul, 2025 - Comments: 0

Synopsys’ Shankar Krishnamoorthy chats with industry experts about how the combination of AI and software-defined systems is driving a re-evaluation of engineering workflows and why chip, software, and system development must evolve in unison. Siemens’ Jake Wiltgen considers the rapidly evolving and growing challenge of performing DFT verification as designs scale, with complex hierarchi... » read more

Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
By Nilesh Kamdar - 02 Jul, 2025 - Comments: 0

After 26 years in the electronics industry, I've witnessed countless technological shifts, but few have been as transformative — or as promising — as what we're experiencing with the CHIPS Act. I spoke at a recent 62nd DAC panel discussion alongside industry colleagues Saverio Fazzari from Booz Allen Hamilton and Vivek Prasad from a non-profit organization established to operate the Nationa... » read more

Rethinking Chip Debug
By Priyank Jain - 30 Jun, 2025 - Comments: 0

The semiconductor industry has spent decades mastering the art of integrated circuit physical verification. But as system-on-chip (SoC) designs push the boundaries of complexity—with more transistors, greater integration and larger silicon areas—the established debug strategies are breaking under the weight of scale. Today’s advanced chips can generate an overwhelming number of design rul... » read more

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures
By Moshiko Emmer - 26 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data,... » read more

Distributing Intelligence Inside Multi-Die Assemblies
By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 26 Jun, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

3D Packaging vs 3D Integration eBook
By Cadence - 25 Jun, 2025 - Comments: 0

In this eBook, you will: •    Explore the background and trends of multi-die packages •    Learn about the distinct approaches of 3D packaging and 3D integration •    Examine the challenges within heterogeneous integration Read more here. » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy