Startup Funding: Q1 2025

By Jesse Allen - 02 Apr, 2025 - Comments: 0

The first quarter of 2025 saw six companies raise at least $100 million in investment. Of those, three went to quantum hardware companies, with major investment into neutral atom, superconducting, and hybrid quantum control approaches. AI chips and enabling technology were another big winner in the quarter, with companies developing optical communications tech for chips and data center infra... » read more

Blog Review: Apr. 2

By Jesse Allen - 02 Apr, 2025 - Comments: 0

Synopsys’ Meenakshy Ramachandran explores how DisplayPort Automotive Extensions help meet functional safety and security standards for the increasingly higher-resolution and more immersive in-vehicle displays in connected, autonomous, shared, and electric vehicles. Siemens’ Gabriella Leone and Michael Munsey discuss the need for a collaborative semiconductor business platform and how to ... » read more

Times Are Changing For EDA

By Brian Bailey - 27 Mar, 2025 - Comments: 1

The EDA industry is about 50 years old, and I see the people responsible for its first generation setting their LinkedIn employment status to 'retired, at home' almost daily. I, for one, have a foot in that camp, but reporting/writing is different than having a full-time job because I can control the time commitment. We have seen many serial entrepreneurs who have created several successful com... » read more

How AI And Connected Workflows Will Close The Verification Bottleneck

By Harry Foster - 27 Mar, 2025 - Comments: 0

For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into the bottleneck of development cycles. This challenge has a name: Verification Productivity Gap 2.0. Back in the early 2000s, the Verification Productivity Gap 1.0 emerged when design complexi... » read more

High-Speed High-Capacity Mixed-Signal Simulation Of Silicon Photonics

By Paul Graykowski - 27 Mar, 2025 - Comments: 0

Many of today’s computing and communications applications demand almost unimaginable processing capability and high-bandwidth access to memory. For example, many data center systems using high-end Graphics Processing Units (GPUs) often need to transfer multiple terabytes per second. Traditional copper-based interconnects, limited to speeds of hundreds of megabits per second (Mbps), cannot ... » read more

Unleashing AI Potential Through Advanced Chiplet Architectures

By Tony Chan Carusone - 27 Mar, 2025 - Comments: 0

The rapid proliferation of machine-generated data is driving unprecedented demand for scalable AI infrastructure, placing extreme pressure on compute and connectivity within data centers. As the power requirements and carbon footprint of AI workloads rise, there is a critical need for efficient, high-performance hardware solutions to meet growing demands. Traditional monolithic ICs will not sca... » read more

Innovating For 6G

By Hwee Yng Yeo - 27 Mar, 2025 - Comments: 0

As the world eagerly anticipates the arrival of applicable 6G innovations, researchers face numerous challenges in validating this next-generation wireless communication technology. The journey from theoretical concepts and mathematical equations to real-world 6G implementation is complex and requires meticulous planning, testing, and measurements to better characterize these ultra-high freque... » read more

Challenges In Managing Chiplet Resources

By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

First-Time Silicon Success Plummets

By Ed Sperling - 27 Mar, 2025 - Comments: 0

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both... » read more

Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs

By Andy Nightingale - 27 Mar, 2025 - Comments: 0

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases lat... » read more

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category: System-Level Design

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