Blog Review: Nov. 20

By Jesse Allen - 20 Nov, 2024 - Comments: 0

Siemens’ Jonathan Muirhead explains why matching and symmetry are so important for analog and RF circuits, especially in topological structures like differential pairs and current mirrors, and introduces checking techniques to ensure compliance. Cadence's Satish Kumar Padhi examines the significance of randomization in PCIe IDE verification, focusing on how it ensures data integrity and en... » read more

Using Formal For RISC-V Security

By Ed Sperling - 19 Nov, 2024 - Comments: 0

Finding and closing up security holes is becoming more important as chips are used in safety- and mission-critical applications, but it's increasingly important for chips designed for much less costly devices, where the selling price typically doesn't warrant a significant investment in security. The problem is these devices are connected to some of the same networks, and any access points for ... » read more

RISC-V’s Software Portability Challenge

By Brian Bailey - 13 Nov, 2024 - Comments: 0

Experts At The Table: RISC-V provides a platform for customization, but verifying those changes remains challenging. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeister, executive director for strategi... » read more

Scaling Performance In AI Systems

By Ed Sperling - 11 Nov, 2024 - Comments: 0

Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

Blog Review: Nov. 6

By Jesse Allen - 06 Nov, 2024 - Comments: 0

Cadence's Satish Kumar C explores how the Deferrable Memory Write transaction type in PCIe and CXL can improve latency, efficiency, and performance by delaying certain memory write operations during system bus congestion or until other priority tasks are complete and highlights implementation and verification challenges. Synopsys' Daryl Seitzer and Rahul Thukral point to magnetoresistive RAM... » read more

Globally Asynchronous, Locally Synchronous Clocks

By Ed Sperling - 04 Nov, 2024 - Comments: 0

Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes ... » read more

Managing Reflections With Terminations

By John Golding - 04 Nov, 2024 - Comments: 0

Have you heard recommendations to use a particular termination in particular situations for good signal integrity? Have you ever wondered how to incorporate terminations in your design? While there are typical use cases for various terminations, sometimes engineers use termination techniques based on a recommendation or assumption that may not work, or at least may not be optimal, for their par... » read more

Why 40G UCIe IP?

By Aparna Tarde - 31 Oct, 2024 - Comments: 0

AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Reducing SoC Power With NoCs And Caches

By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Chiplets Make Progress Using Interconnects As Glue

By Ann Mutschler - 31 Oct, 2024 - Comments: 0

Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: System-Level Design

category: IoT, Security & Automotive