category: System-Level Design

category: IoT, Security & Automotive

Blog Review: June 4
By Jesse Allen - 04 Jun, 2025 - Comments: 0

In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the implications of the software-defined transition, how it affects semiconductor development, and why it seems to be leading more companies towards developing their own silicon. Cadence’s Vinod Khera shows off a Linux-based audio development platform for prototyping AI audio applications with support for real-time ... » read more

Mastering Chiplet Design
By Michelle Clancy Fuller - 03 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a fundamental shift from monolithic chip designs to chiplet-based architectures. This modular approach promises enhanced performance, cost efficiency, and scalability, but it also brings unique system-level verification challenges that design teams must overcome. Chiplet systems break different functions into smaller, separate dies, improving yield an... » read more

Accelerating Scalable Computing
By Shivi Arora - 02 Jun, 2025 - Comments: 0

By Shivi Arora and Sue Hung Fung As computing demands for HPC, AI/ML, and cloud infrastructure grow, modular architectures are replacing traditional monolithic System-on-Chip (SoC) designs. These legacy designs are increasingly expensive and difficult to scale due to ever-increasing silicon complexity. In response, the industry is embracing chiplet-based System-in-Package (SiP) solutions,... » read more

The DAC Valuation
By Brian Bailey - 29 May, 2025 - Comments: 1

The Design Automation Conference is approaching fast, and the evidence of a funding gap is in plain sight. An entire day of the technical conference has been dropped. This is disheartening to say the least, and in the long term it may be a very costly mistake. The problems started when the Internet bubble burst in 2000. Until then, DAC was growing to the point whereby few convention halls we... » read more

Addressing Stress In Heterogeneous 3D-IC Designs
By Shetha Nolke - 29 May, 2025 - Comments: 0

The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Closing The RISC-V Verification Disconnect
By Larry Lapides - 29 May, 2025 - Comments: 0

With the explosive adoption of RISC-V processors, processor verification has become a hot topic. This is due both to the criticality of the processor IP in the SoC and to the fact that many experienced SoC verification engineers are doing their first processor verification project. While there are similarities between SoC verification and processor verification, there are also significant diffe... » read more

Optimizing Data Movement
By Ann Mutschler - 29 May, 2025 - Comments: 1

Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

Boosting AI Performance With CXL
By Vanessa Do - 29 May, 2025 - Comments: 0

As AI applications rapidly advance, AI models are being tasked with processing massive amounts of data containing billions – or even trillions – of parameters. Each large workload involves numerous iterations for data comparison, predictive calculations, and parameter results updating during training. Hence, there is a constant demand for flexible memory expansion and memory sharing among d... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 0

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

Executive Outlook: Chiplets, 3D-ICs, and AI
By Ed Sperling - 29 May, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss chiplets and the challenges of moving to 3D-ICs with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy