category: System-Level Design

category: IoT, Security & Automotive

Blog Review: Nov. 10
By Jesse Allen - 10 Nov, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Malcolm Penn of Future Horizons explains key reasons behind the cyclical nature of the semiconductor industry and how the root of the current chip shortage problems goes back to before the pandemic. Siemens EDA's Ray Salemi continues investigating using Python for verification with a look at some UVM utilities and how they would be used in Python. Syn... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Nov, 2021 - Comments: 0

Business Synopsys acquired Concertio, a provider of AI-powered performance optimization software. The acquisition will bolster Synopsys' silicon lifecycle management platform SiliconMAX SLM with the addition of Concertio's autonomous software agent that, when installed on the target system, continuously monitors the interactions between operating applications and the underlying system enviro... » read more

Blog Review: Nov. 3
By Jesse Allen - 03 Nov, 2021 - Comments: 0

In a blog for Arm, Matthew Griffin of the 311 Institute warns that cybersecurity is an increasingly pressing problem, with large criminal organizations raking in large sums of money and attacks able to impact a wide range of physical systems. Cadence's Paul McLellan checks out Google's video encoder chip and how it helps lower the CPU recycles required by the vast number of videos uploaded t... » read more

What’s Missing For Designing Chips At The System Level
By Ed Sperling - 01 Nov, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Oct, 2021 - Comments: 0

Arteris IP uncorked its initial public offering this week, a rare occurrence for a semiconductor IP vendor over the past couple decades. The stock began trading on the Nasdaq Global Market on Wednesday under the ticker symbol AIP, gaining more than 40% on its first day. Tools Codasip updated its Studio processor design toolset. Version 9.1 includes an expanded bus support with full AXI for ... » read more

Dealing With Market Shifts
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Back in the days when I was in EDA development, I was taken in by the words of Clayton Christensen when he published "The Innovators Dilemma." He successfully introduced the technology world to the ideas of disruptive innovation. One of the key takeaways was that you should always be working to make your own successful products redundant, or someone else will do it for you. One tool I worked... » read more

What’s Next For Emulation
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Emulation is now the cornerstone of verification for advanced chip designs, but how emulation will evolve to meet future demands involving increasingly dense, complex, and heterogeneous architectures isn't entirely clear. EDA companies have been investing heavily in emulation, increasing capacity, boosting performance, and adding new capabilities. Now the big question is how else they can le... » read more

Functional Safety Across Analog And Digital Domains
By Frank Schirrmeister - 28 Oct, 2021 - Comments: 1

The autonomy of vehicles has been all the rage recently. There are different levels of autonomous driving, with level 5 “Full Automation” being the target the industry is working towards, and Level 2 “Partial Automation” and Level 3 “Conditional Automation” being the level at which the automotive sector currently delivers the most technology. The amount of electronics in cars has be... » read more

Partitioning For Better Performance And Power
By Ann Mutschler - 28 Oct, 2021 - Comments: 0

Partitioning is becoming more critical and much more complex as design teams balance different ways to optimize performance and power, shifting their focus from a single chip to a package or system involving multiple chips with very specific tasks. Approaches to design partitioning have changed over the years, most recently because processor clock speeds have hit a wall while the amount of d... » read more

High-Level Synthesis For RISC-V
By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

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