category: System-Level Design

category: IoT, Security & Automotive

Blog Review: June 24
By Jesse Allen - 24 Jun, 2020 - Comments: 0

Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

Eliminate Silicon Respins With Netlist CDC Verification
By Synopsys - 24 Jun, 2020 - Comments: 0

Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Jun, 2020 - Comments: 0

Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Blog Review: June 17
By Jesse Allen - 17 Jun, 2020 - Comments: 0

Mentor's Chris Spear provides an introduction to SystemVerilog Multidimensional Arrays and shares code samples to follow along. Cadence's Paul McLellan listens in on Sophie Wilson's 2020 Wheeler Lecture that traces the history of the microprocessor from the early days of Moore's Law through to increasing power and economic constraints that are causing a transition from general purpose to spe... » read more

Simplifying And Speeding Up Verification
By Ed Sperling - 16 Jun, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Imagination’s Approach To Business In China
By Woz Ahmed - 16 Jun, 2020 - Comments: 0

In my role as Imagination’s CSO, I have been asked several times today whether Imagination would hive off its China operations into a China JV. My first response to this question is “Why?” And this generates several responses.  The conversation goes something like this: “Because you have to!” No, not at all. Nobody has asked us to do that – we can transact business in China ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Jun, 2020 - Comments: 0

Synopsys acquired Qualtera, a provider of big data analytics for semiconductor test and manufacturing. Based in Montpellier, France and founded in 2010, Qualtera's Silicondash platform provides both off-line and in-line modules for data analytics, visualization, simulation, and modeling to allow for development of control strategies. Combined with Synopsys' TestMAX test automation solution, the... » read more

Blog Review: June 10
By Jesse Allen - 10 Jun, 2020 - Comments: 0

Cadence's Paul McLellan considers the issues around benchmarking neural networks running on different hardware and challenges in comparing designs. Mentor's Shivani Joshi points to a few of the different types of jitter and some key factors to review when trying to limit jitter. Synopsys' Fred Bals notes that while the National Vulnerability Database is a good source for information on public... » read more

Configuring Processors In The Field
By Brian Bailey - 08 Jun, 2020 - Comments: 0

The convergence of two technologies, extensible processors and embedded FPGAs, is enabling the creation of processors that can be dynamically configured in the field. But it's not clear if there is a need for them or how difficult would it be to program them. This remains an open question even though there is evidence of its usefulness in the past and new products are expected to reach the mark... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Jun, 2020 - Comments: 1

Tools & IP Synopsys introduced its DesignWare USB4 IP solution consisting of controllers, routers, PHYs, and verification IP. It supports USB4, DisplayPort with HDCP 2.3 security, PCI Express, and Thunderbolt 3 connectivity protocols through USB Type-C connectors and cables. The USB4 IP operates at up to 40 Gbps, twice the maximum data rate of USB 3.2, and is backwards compatible with USB 3... » read more

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