category: System-Level Design

category: Auto, Security & Edge AI

Week In Review: Design, Low Power
By Jesse Allen - 16 Apr, 2021 - Comments: 0

Siemens Digital Industries Software will acquire OneSpin Solutions, a provider of formal verification tools. The company's portfolio of formal tools and apps covers a wide range of design verification, equivalence checking, and functional safety, as well as solutions for trust and security checking. Siemens plants to add OneSpin's technology to the Xcelerator portfolio of verification tools. ... » read more

Blog Review: April 14
By Jesse Allen - 14 Apr, 2021 - Comments: 0

Siemens EDA's Jake Wiltgen provides an overview of setting up an executing a fault injection campaign to prove that the IC or IP will safely operate under a faulted state caused by a random hardware failure, required to meet higher ASIL targets for ISO 26262 functional safety certification. Synopsys' Taylor Armerding considers the state of medical device security and the growing attack surfa... » read more

EDA, IP Revenues Soar
By Ed Sperling - 13 Apr, 2021 - Comments: 1

EDA and IP revenues increased 15.4% to $3.032 billion in Q4 2020, according to a just-released report, with huge increases reported in China and India, and a solid double-digit increase in the Americas. EDA/IP revenue from China increased 66.4% in Q4 EDA/IP compared with the same period in 2019, and for the 2020 calendar year it was up 52.3%. India's spending was up 32% for the quarter. And ... » read more

Requirements For Exhaustive SoC Reset Domain Crossing Checks
By Joe Mallett - 13 Apr, 2021 - Comments: 0

It is common to read that the numbers of clock domains and power domains in system-on-chip (SoC) designs are increasing, but for some reason there is less discussion about resets. There is no doubt that the number of reset domains is also rising; studies have shown that the single reset of twenty years ago has been replaced by a complex network of 40-50 domains in many chips and even 150 in som... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Apr, 2021 - Comments: 0

Tools & IP Cadence debuted the Palladium Z2 Enterprise Emulation and Protium X2 Enterprise Prototyping systems. The Palladium Z2 is based on a new custom emulation processor, while the Protium X2 is based on Xilinx UltraScale+ VU19P FPGAs. Designed to work together with a common front-end flow, they provide 2X capacity and 1.5X performance improvements over the previous generations, and ne... » read more

Blog Review: April 7
By Jesse Allen - 07 Apr, 2021 - Comments: 0

Cadence's Paul McLellan checks out the US National Security Commission on Artificial Intelligence report and what it recommends for funding the development of AI as well as semiconductor manufacturing and research. Siemens EDA's Ray Salemi continues exploring Python for verification and shows how to use cocotb to create a simple bus functional model and connect it to a testbench. Synopsys... » read more

Finding And Fixing Design And Testbench Coding Errors On The Fly
By Synopsys - 06 Apr, 2021 - Comments: 0

Two things are certain in chip verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. It is preferable that many classes of err... » read more

Week In Review: Design, Low Power
By Jesse Allen - 02 Apr, 2021 - Comments: 0

Magnachip will be acquired by Wise Road Capital for $1.4 billion, taking the NYSE-listed company private. The company designs and manufactures OLED display driver ICs and a range of power management discretes and ICs. Magnachip's management team and employees are expected to continue in their roles, and the company will remain based in Cheongju, Seoul, and Gumi, South Korea. The all-cash transa... » read more

How Heterogeneous ICs Are Reshaping Design Teams
By Ed Sperling - 31 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the complex interactions developing between different engineering groups as designs become more heterogeneous, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Mai... » read more

Blog Review: March 31
By Jesse Allen - 31 Mar, 2021 - Comments: 0

Arm's Pavel Rudko considers several common approaches used to get better performance for neural network inference on mobile devices, such as optimizing and pruning the model and using different processing units to execute different workloads in parallel. Siemens EDA's Ray Salemi introduces basic concepts of using Python for verification and how to get Python to talk to an RTL device-under-te... » read more

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