Week In Review: Design, Low Power

Acquisitions galore: Siemens-OneSpin, Synopsys-MorethanIP, Cadence-Pointwise; processor design toolset; IP for functional safety; PSS 2.0.


Siemens Digital Industries Software will acquire OneSpin Solutions, a provider of formal verification tools. The company’s portfolio of formal tools and apps covers a wide range of design verification, equivalence checking, and functional safety, as well as solutions for trust and security checking. Siemens plants to add OneSpin’s technology to the Xcelerator portfolio of verification tools.

“OneSpin Solutions has been dedicated to solving the most difficult verification challenges to assure IC integrity. Our unique technology and focus have fueled our record growth across a number of domains including 5G, automotive, datacenter, IoT, and aerospace/defense,” said Raik Brinkmann, president and CEO at OneSpin Solutions. “Being part of Siemens will allow us to accelerate technology development and deliver our much-needed solutions to a broader user base with the goal of becoming the market’s leading formal verification provider.” Based in Munich, Germany, OneSpin was founded in 2005. Terms of the deal, which was struck with the company’s primary investor Azini Capital, were not disclosed. It is expected to close in Q2 2021.

Synopsys will acquire MorethanIP, a provider of Ethernet Digital Controller IP supporting data rates from 10G to 800G. The acquisition adds MAC (Medium Access Controller) and PCS (Physical Coding Sublayer) for 200G/400G and 800G Ethernet to Synopsys’ portfolio. The company also provides Time-Sensitive Networking, Fibre Channel, and Ethernet Switching IP for integration into ASICs and FPGAs. MorethanIP was founded in 2000 and is based in Karlsfeld, Germany. Terms of the deal were not disclosed. It is expected to close in May 2021.

Cadence acquired Pointwise, a provider of mesh generation software for computational fluid dynamics (CFD). The software covers all aspects of preprocessing from geometry model import to flow solver export and allows for generation of structured, overset, unstructured, high-order and hybrid meshes. Cadence noted that it complements the technology of NUMECA, another recent CFD acquisition. Pointwise’s origins came from the Gridgen meshing software in 1984, the development of which was funded by the United States Air Force, and NASA Langley and Ames Research Centers. Gridgen was privatized in 1994, leading to the creation of Pointwise. It was based in Fort Worth, Texas. Terms of the deal were not disclosed.

Codasip unveiled the Codasip Studio 9.0 processor design toolset and Codasip CodeSpace 9.0 embedded software development platform. Studio 9.0 features an improved LLVM-based SDK including a fast C/C++ compiler, assembler, disassembler, and linker, with advanced support for debugging (DWARF format), and support for new ELF formats. Both products include the Linker Support Package, an interface for developing linker scripts, which represent a system memory map. Also new is a tutorial 32-bit/64-bit uRISC-V processor.

S2C released Prodigy Multi-Debug Module Pro, an upgrade to Prodigy MDM, which aims to shorten the debug process for FPGA prototyping. The new release provides deeper trace to store up to 64GB of waveforms, faster sampling rate of up to 125MHz, faster bandwidth to support simultaneous debug of up to 8 FPGAs and new features such as dynamic probing to enable readback of internal DFF/BRAM values and advance triggers. MDM Pro currently supports trace up to 16K probes per FPGA in 8 groups of 2K probes without re-compile. Future software update is expected to expand to 64K probes in 8 groups of 8K.

Synopsys debuted DesignWare tRoot Hardware Secure Module (HSM) and ARC SEM130FS Safety and Security Processor IP to support ISO 26262 certification. The tRoot HSM for Automotive is ASIL B compliant and adds hardware safety mechanisms for protection against permanent, transient, and latent faults to its security system that includes an ARC processor, scalable side-channel resistant cryptography, true random number generator and security-enabled external memory controllers. The ARC SEM130FS Processor is ASIL D compliant and adds safety-critical hardware features such as dual-core lockstep to meet automotive safety requirements.

Avery Design Systems revealed its CXL 2.0 system-level VIP simulation solution. It supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP to enable pre-silicon hardware-software validation of CXL 2.0 Type 3 memory expansion system designs.

AnalogX uncorked a 1-40G 22nm SerDes platform consuming less than 2pJ/bit. The SerDes IP supports 5G radio needs such as JESD204 and CPRI, and also supports PCIe, CXL, CCIX, and Ethernet applications. It is designed to pass automotive design rules and suitable for use in low orbit space communication applications.

H3C Semiconductor used Ansys’ simulation tools in developing its ENGIANT 660 network processor chip for routing, AI, 5G backhaul, and cybersecurity applications. Ansys tools were used to perform analysis of power noise, signal integrity, thermal reliability, and structural dependability from chip design to signoff. H3C Semiconductor cited reduced hardware costs and increased production speed.

Renesas adopted Synopsys’ DSO.ai AI design space optimization system for its automotive chip design environment. Renesas cited the ability to explore a larger scale of choices in existing chip design workflows and meet PPA targets.

Mavenir and Xilinx are working on a unified 4G/5G O-RAN massive MIMO (mMIMO) portfolio to enable Open RAN deployments. The two companies have completed end-to-end integration of a first-generation mMIMO solution using Open RAN principles, which was evaluated by six CSPs. Mavenir delivered the Virtualized RAN (vRAN) support for mMIMO, including Core Network, CU and DU, with Xilinx providing the Category B O-RAN Radio Unit. The first mMIMO 64TRX joint solution is expected to be available in Q4 2021.

Velodyne and Ansys are collaborating to develop software models of next-generation automotive lidar sensors to provide improved hazard identification capabilities for autonomous vehicles. Velodyne’s lidar design has been incorporated into Ansys’ virtual sensor suite to expedite automakers’ integration of the sensor.

Accellera published the Portable Test and Stimulus Standard 2.0. New language features in the second edition include a core library for standard portable functionality and utilities for common PSS applications, a core library for mapping scenario elements to execution agents in the target implementation, collection types, parameterized lists, constraint enhancements, improved activity-level generation and scheduling constructs, and portability of procedural constructs. The standard is available for free.

EDA and IP revenues increased 15.4% to $3.032 billion in Q4 2020, according to the ESD Alliance. The four-quarter moving average rose by 11.6%, the highest annual growth since 2011 and the second highest in the last 14 years. IC physical design and verification saw the largest growth, with revenue increasing 36.6% to $637.1 million compared to Q4 last year. IP revenue was up 16.9% to $1.053 billion, followed by CAE with an increase of 9.4% to $956.9 million.

Revenue from China and India both saw sizeable gains, 66.4% and 32% in Q4, respectively. A record 48,478 people were employed in the industry, up 6.7% over the same period in 2019, and up 3% from the fourth quarter of 2020. Read more details in EDA, IP Revenues Soar.

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The Linley Spring Processor Conference 2021 will take place April 19-23. On April 20-22, several events will take place: Synopsys’ SNUG World, Ansys’ Simulation World, and the Industry Strategy Symposium Europe 2021. The IEEE Custom Integrated Circuits Conference (CICC 2021) will close out the month on April 25-30.

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