RISC-V Targets Data Centers


RISC-V vendors are beginning to aim much higher in the compute hierarchy, targeting data centers and supercomputers rather than just simple embedded applications on the edge. In the past, this would have been nearly impossible for a new instruction set architecture. But a growing focus on heterogeneous chip integration, combined with the reduced benefits of scaling and increasing demand for ... » read more

What Is Silicon Lifecycle Management? A Strategic Imperative


The recent buzz about silicon lifecycle management speaks to the boom in high-stakes electronic devices. Whether it is an SoC used in a vehicle or in the datacenter, there are compelling reasons to monitor and analyze data regarding the design, realization, deployment, and field service of the device. While silicon lifecycle management is an emerging paradigm in the semiconductor industry, i... » read more

What Is An ASIP?


ASIP stands for “application-specific instruction-set processor” and simply means a processor which has been designed to be optimal for a particular application or domain. General-purpose versus application- or domain-specific processors Most processor cores to date have been general-purpose, which means that they have been designed to handle a wide range of applications with good average... » read more

Cross Spectrum Video Processing


While immunization vaccines are rolling out at an impressive pace, and as society slowly reopens, our best defense against the Coronavirus continues to be early detection and rapid response (such as self-isolation). An early symptom of having the virus is an increased body temperature, which can be easily measured using contactless methods such as thermal sensors or cameras sensitive to IR r... » read more

Enabling The Next Step In IC Test And Monitoring


Product lifecycle management (PLM) is a well-established concept across many industries that aims to manage the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. More recently, these principles are being applied by the semiconductor industry because electronics continue to p... » read more

Blog Review: April 21


Synopsys' Taylor Armerding warns that without making cybersecurity a priority, companies may be positioning themselves as the weak link in the supply chain, and provides some tips for protecting both the company and its customers. Siemens EDA's Simon Favre points to critical area analysis and design for manufacturing as two important strategies to improve IC yield and quality. Cadence's P... » read more

Early, Accurate, Signoff-Correlated Power Analysis


Power estimation has always been a fundamental part of semiconductor development, but it has grown in importance in recent years. Virtually every application domain has power limitations that must be satisfied before a chip is fabricated. There is no effective way to fix power issues in the lab or in the field, so pre-silicon estimation must be accurate. The short development cycles for many ty... » read more

Best Practices For Efficient And Effective Planar EM Simulation


Designers of today’s complex, multi-featured communications products require accurate and fast electromagnetic (EM) simulation to deliver cost-effective, high-performance products to market in ever-shrinking windows of opportunity. The Cadence AWR AXIEM 3D planar method-of-moments (MoM) EM analysis simulator within the AWR software portfolio delivers the accuracy, capacity, and speed designer... » read more

What You Should Consider When Choosing A Processor IP Core


Most integrated circuits include at least one processor core and some embedded software. In the case of more complex systems-on-chip (SoC), there may be application processors running the main software, and operating system plus multiple specialised subsystems handling functions such as communications, security, and sensors. Requirements for processing vary considerably and there is a wide choi... » read more

Next-Gen Design Challenges


As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

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