category: Architectures

category: IoT, Security & Automotive

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design
By Technical Paper Link - 14 Dec, 2022 - Comments: 0

A new technical paper titled "A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems" was published by researchers at Hongik University, Seoul, South Korea. "An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digi... » read more

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

Leveraging Multi-Agent RL for Microprocessor Design Space (Harvard, Google)
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A new technical paper titled "Multi-Agent Reinforcement Learning for Microprocessor Design Space Exploration" was published by researchers at Harvard University and Google research groups. Abstract "Microprocessor architects are increasingly resorting to domain-specific customization in the quest for high-performance and energy-efficiency. As the systems grow in complexity, fine-tuning arch... » read more

Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)
By Technical Paper Link - 12 Dec, 2022 - Comments: 0

A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

HW-Enabled Security Techniques To Improve Platform Security And Data Protection For Cloud Data Centers And Edge Computing (NIST)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A technical paper titled "Hardware-Enabled Security: Enabling a Layered Approach to Platform Security for Cloud and Edge Computing Use Cases" was published by NIST, Intel, AMD, Arm, IBM, Cisco and Scarfone Cybersecurity. Abstract: "In today’s cloud data centers and edge computing, attack surfaces have shifted and, in some cases, significantly increased. At the same time, hacking has becom... » read more

HW Accelerator Architecture for MI Computation With Low Latency, Energy Efficient (MIT)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A new technical paper titled "Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time" was published by researchers at MIT. Find the technical paper here. "In this paper, we introduce a new hardware accelerator architecture for MI computation that features a low-latency, energy-efficient MI compute core and an optimized memory subsystem that provides sufficie... » read more

Using Sparseloop in Hardware Accelerator Design Flows (MIT)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling" was published by researchers at MIT and NVIDIA.  The paper won "Distinguished Artifact Award" at the MICRO 2022 conference. Find the technical paper here.  Published 2022.  Project website is here and github here. Abstract: "In recent years, many accelerators have been proposed to effici... » read more

Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation" was published by researchers at MIT (CSAIL), Argonne National Lab, and TU Munich. The paper was a Best Paper Finalist and a Best Student Paper winner at SuperComputing 2022. Find the technical paper here. Published November 2022. The work "demonstrates how Enzyme opti... » read more

Profile-Guided HW/SW Mechanism To Efficiently Reduce Branch Mispredictions In Data Center Applications (Best Paper Award)
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications" was published by researchers at University of Michigan, ARM, University of California, Santa Cruz, and Texas A&M University. This work was awarded a best paper award at October's 2022 Institute of Electrical and Electronics Engineers (IEEE)/Association for Computing Machin... » read more

Approximate Adders Suitable For In-Memory Computing Using a Memristor Crossbar Array
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "IMAGIN: Library of IMPLY and MAGIC NOR Based Approximate Adders for In-Memory Computing" was published by researchers at DFKI (German Research Center for Artificial Intelligence) and Indian Institute of Information Technology Guwahati. "We developed a framework to generate approximate adder designs with varying output errors for 8, 12, and 16-bit adders. We imp... » read more

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