category: Architectures

category: IoT, Security & Automotive

Memory and Energy-Efficient Batch Normalization Hardware
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training" was published by researchers at DGIST (Daegu Gyeongbuk Institute of Science and Technology). The work was supported by Samsung Research Funding Incubation Center. Abstract: "When training early-stage deep neural networks (DNNs), generating intermediate features via con... » read more

Multi-Bit In-Memory Computing System for HDC using FeFETs, Achieving SW-Equivalent-Accuracies
By Technical Paper Link - 11 Nov, 2022 - Comments: 0

A new technical paper titled "Achieving software-equivalent accuracy for hyperdimensional computing with ferroelectric-based in-memory computing" by researchers at University of Notre Dame, Fraunhofer Institute for Photonic Microsystems, University of California Irvine, and Technische Universität Dresden. "We present a multi-bit IMC system for HDC using ferroelectric field-effect transistor... » read more

Energy of Computing As A Key Design Aspect (SLAC/Stanford, MIT)
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Trends in Energy Estimates for Computing in AI/Machine Learning Accelerators, Supercomputers, and Compute-Intensive Applications" was published by researchers at SLAC/Stanford University and MIT. Abstract: "We examine the computational energy requirements of different systems driven by the geometrical scaling law, and increasing use of Artificial Intelligence or Ma... » read more

Scalable Optical AI Accelerator Based on a Crossbar Architecture
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration" was published by researchers at University of Washington. Abstract: "Optical computing has been recently proposed as a new compute paradigm to meet the demands of future AI/ML workloads in datacenters and supercomputers. However, proposed implementations so far suffer from lack of sc... » read more

L-FinFET Neuron For A Highly Scalable Capacitive Neural Network (KAIST)
By Technical Paper Link - 31 Oct, 2022 - Comments: 0

A new technical paper titled "An Artificial Neuron with a Leaky Fin-Shaped Field-Effect Transistor for a Highly Scalable Capacitive Neural Network" was published by researchers at KAIST (Korea Advanced Institute of Science and Technology). “In commercialized flash memory, tunnelling oxide prevents the trapped charges from escaping for better memory ability. In our proposed FinFET neuron, t... » read more

Side-Channel Secure Translation Lookaside Buffer Architecture
By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A new technical paper titled "Risky Translations: Securing TLBs against Timing Side Channels" was posted by researchers at Ruhr University Bochum (Germany) and Cyber-Physical Systems of the German Research Center for Artificial Intelligence (DFKI). Abstract: "Microarchitectural side-channel vulnerabilities in modern processors are known to be a powerful attack vector that can be utilized to... » read more

In-NAND Flash Processing Technique for Improved Performance, Energy Efficiency & Reliability of Bulk Bitwise Operations
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new technical paper titled "Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory" was published by researchers at ETH Zurich, POSTECH, LIRMM/Univ. Montpellier/CNRS and Kyungpook National University. Find the technical paper here (published September 2022) and related YouTube lecture here. "We propose Flash-Cosmos (Flash Computation wi... » read more

Using Silicon Photonics To Reduce Latency On Edge Devices
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new technical paper titled "Delocalized photonic deep learning on the internet’s edge" was published by researchers at MIT and Nokia Corporation. “Every time you want to run a neural network, you have to run the program, and how fast you can run the program depends on how fast you can pipe the program in from memory. Our pipe is massive — it corresponds to sending a full feature-leng... » read more

Technical and Structural Approaches To Centralize Automotive E/E Architectures
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A technical paper titled "Methodical Approach for Centralization Evaluation of Modern Automotive E/E Architectures" was published by researchers at University of Stuttgart and Daimler Truck AG. Abstract: "Centralization is considered as a key enabler to master the CPU-intensive features of the modern car. The development and architecture change towards the next generation car is influenced ... » read more

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System
By Technical Paper Link - 24 Oct, 2022 - Comments: 0

A technical paper titled "RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory" was published by researchers at ETH Zürich, KMUTNB, NTUA, and University of Toronto. Abstract: "Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-graine... » read more

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