category: Manufacturing

category: IoT, Security & Automotive

Addressing The Challenge Of Metallization In Highly Integrated (3D) Stretchable Electronics
By Technical Paper Link - 27 Jun, 2023 - Comments: 0

A technical paper titled “Scalable electrodeposition of liquid metal from an acetonitrile-based electrolyte for highly-integrated stretchable electronics” was published by researchers at KU Leuven. Abstract: "For the advancement of highly-integrated stretchable electronics, the development of scalable sub-micrometer conductor patterning is required. Eutectic gallium indium EGaIn is an att... » read more

Search Based Method For Identifying Aging Model Parameters
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology” was published by researchers at University of Victoria. Abstract: "The design of countermeasures against integrated circuit counterfeit recycling requires the ability to simulate aging in CMOS devices. Electronic design automation tools commonly provide this ability... » read more

Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

3D Memory Structures: Common Hole And Tilt Metrology Techniques and Capabilities
By Technical Paper Link - 03 Jun, 2023 - Comments: 0

A technical paper titled "Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering" was published by researchers at Bruker Nano and Lam Research. Abstract: "High aspect ratio (HAR) structures found in three-dimensional nand memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep... » read more

Latest Discoveries in the Mechanics of 2D Materials
By Technical Paper Link - 31 May, 2023 - Comments: 0

A new technical paper titled "Recent advances in the mechanics of 2D materials" was published by researchers at McGill University, University of Science and Technology of China, and University of Illinois. "We review significant advances in the understanding of the elastic properties, in-plane failures, fatigue performance, interfacial shear/friction, and adhesion behavior of 2D materials. I... » read more

ALD-Oxide Semiconductors: Summary, Benefits And Challenges
By Technical Paper Link - 31 May, 2023 - Comments: 0

A technical paper titled "Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook" was published by researchers at Hanyang University. "In this review, to introduce ALD-oxide semiconductors, we provide: (a) a brief summary of the history and importance of ALD-based oxide semiconductors in industry, (b) a discussion of the benefits of ALD for oxide... » read more

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs
By Technical Paper Link - 19 May, 2023 - Comments: 0

A new technical paper titled "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing" was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute of Technology Kanpur, and TU Munich, with funding by the German Research Foundation. Abstract "In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Deplet... » read more

28nm-HKMG-Based FeFET Devices For Synaptic Applications
By Technical Paper Link - 09 May, 2023 - Comments: 0

A technical paper titled "28 nm high-k-metal gate ferroelectric field effect transistors based synapses- A comprehensive overview" was published by researchers at Fraunhofer-Institut für Photonische Mikrosysteme IPMS, Indian Institute of Technology Madras, and GlobalFoundries. Abstract This invited article we present a comprehensive overview of 28 nm high-k-metal gate-based ferroelectric f... » read more

Reconfigurability and NTC-based Signal Modulation Within a Single Ferroelectric TFET
By Technical Paper Link - 09 May, 2023 - Comments: 0

A new technical paper titled "Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor" was published by researchers at Lund University in Sweden. Abstract: "Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we ... » read more

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