Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)


A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

Effects of Size Scaling and Device Architecture on the Radiation Response of Nanoscale MOS Transistors


A new technical paper titled "Perspective on radiation effects in nanoscale metal–oxide–semiconductor devices" was published by a researcher at Vanderbilt University, Nashville, Tennessee. The work was partially supported by the Defense Threat Reduction Agency and by the U.S. Air Force Office of Scientific Research and Air Force Research Laboratory. According to the paper, "this Perspect... » read more

State Of The Art And Recent Progress of Reconfigurable Electronic Devices Based on 2D Materials


A new technical paper titled "Emerging reconfigurable electronic devices based on two-dimensional materials: A review" was just published by researchers at TU Dresden, NaMLAb gGmbH, and RWTH Aachen University. Abstract "As the dimensions of the transistor, the key element of silicon technology, are approaching their physical limits, developing semiconductor technology with novel concepts an... » read more

Beyond 5nm: Review of Buried Power Rails & Back-Side Power


A new technical paper titled "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes" is presented by researchers at UT Austin, Arm Research, and imec. Find the technical paper here. Published July 2022. S. S. T. Nibhanupudi et al., "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes," in IEEE Transactions... » read more

Reporting and Benchmarking Process For A 2D Semiconductor FET


New research paper titled "How to Report and Benchmark Emerging Field-Effect Transistors" was published from researchers at NIST, Purdue University, UCLA, Theiss Research, Peking University, NYU, Imec, RWTH Aachen, and others. "Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and compar... » read more

Define & Grow III–V Vertical Nanowires At A High Footprint Density on a Si Platform


New technical paper titled "Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition" is published from researchers at Lund University in Sweden. Abstract: "Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost-effective proc... » read more

Identifying PCB Defects with a Deep Learning Single-Step Detection Model


This new technical paper titled "End-to-end deep learning framework for printed circuit board manufacturing defect classification" is from researchers at École de technologie supérieure (ÉTS) in Montreal, Quebec. Abstract "We report a complete deep-learning framework using a single-step object detection model in order to quickly and accurately detect and classify the types of manufacturi... » read more

Publicly Available Dataset for PCB X-Ray Inspection (FICS- University of Florida)


Researchers from the Florida Institute for Cybersecurity (FICS) at the University of Florida published this technical paper titled "FICS PCB X-ray: A dataset for automated printed circuit board inter-layers inspection." Abstract "Advancements in computer vision and machine learning breakthroughs over the years have paved the way for automated X-ray inspection (AXI) of printed circuit bo... » read more

Film Failure in Multilayer Systems for Semiconductor Devices


Researchers at MIT, Yonsei University (Seoul, Korea) just published this technical paper titled "Interfacial Delamination at Multilayer Thin Films in Semiconductor Devices." According to the abstract "In this work, the effect of thermomechanical stress on the failure of multilayered thin films on Si substrates was studied using analytical calculations and various thermomechanical tests." ... » read more

FEOL Nanosheet Process Flow & Challenges Requiring Metrology Solutions (IBM Watson)


New technical paper titled "Review of nanosheet metrology opportunities for technology readiness," from researchers at IBM Thomas J. Watson Research Ctr. (United States). Abstract (partial): "More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. T... » read more

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