category: Memory

category: IoT, Security & Automotive

Heterogeneous Ultra-Low-Power RISC-V SoC Running Linux
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A technical paper titled "HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC" was published by researchers at University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich. "We present HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a 64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator (PMCA), delivering up to... » read more

Leveraging Multi-Agent RL for Microprocessor Design Space (Harvard, Google)
By Technical Paper Link - 13 Dec, 2022 - Comments: 0

A new technical paper titled "Multi-Agent Reinforcement Learning for Microprocessor Design Space Exploration" was published by researchers at Harvard University and Google research groups. Abstract "Microprocessor architects are increasingly resorting to domain-specific customization in the quest for high-performance and energy-efficiency. As the systems grow in complexity, fine-tuning arch... » read more

2D-Materials-Based Electronic Circuits (KAUST and TSMC)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A special edition article titled "Electronic Circuits made of 2D Materials" was just published by Dr. Mario Lanza, KAUST Associate Professor of Material Science and Engineering, and Iuliana Radu, corporate researcher at TSMC. This special issue covers 21 articles from leading subject matter experts, ranging from materials synthesis and their integration in micro/nano-electronic devices and c... » read more

Fabricating FeFET Devices with Silicon-Doped Hafnium Oxide As A Ferroelectric Layer
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A new technical paper titled "Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications" was published by researchers at Fraunhofer IPMS, GlobalFoundries, and TU Bergakademie Freiberg. Abstract (partial) "This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

HW Accelerator Architecture for MI Computation With Low Latency, Energy Efficient (MIT)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A new technical paper titled "Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time" was published by researchers at MIT. Find the technical paper here. "In this paper, we introduce a new hardware accelerator architecture for MI computation that features a low-latency, energy-efficient MI compute core and an optimized memory subsystem that provides sufficie... » read more

MAC Operation on 28nm High-k Metal Gate FeFET-based Memory Array with ADC (Fraunhofer IPMS/GF)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array" was published by researchers at Fraunhofer IPMS and GlobalFoundries. Abstract "This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric fi... » read more

Capability Hardware Enhanced RISC Instructions (CHERI) For Verification, With Better Memory Safety (Oxford)
By Technical Paper Link - 30 Nov, 2022 - Comments: 0

A technical paper titled "A Formal CHERI-C Semantics for Verification" was published by researchers at University of Oxford. Abstract: "CHERI-C extends the C programming language by adding hardware capabilities, ensuring a certain degree of memory safety while remaining efficient. Capabilities can also be employed for higher-level security measures, such as software compartmentalization, ... » read more

Rowhammer: Recent Developments & Future Directions (ETH Zurich)
By Technical Paper Link - 20 Nov, 2022 - Comments: 0

A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract: "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon i... » read more

High Performance Memory: Novel Lateral Double Magnetic Tunnel Junction (MTJ) With An Orthogonal Polarizer
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory" was published by researchers at Hanyang University. Find the technical paper here. Published November 2022. Sin, S., Oh, S. Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory.... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy