category: Packaging

category: IoT, Security & Automotive

Topology for Substrate Routing in Semiconductor Package Design
By Technical Paper Link - 15 Feb, 2022 - Comments: 0

Abstract: In this work, we propose a new signal routing method for solving routing problems that occur in the design process of semiconductor package substrates. Our work uses a topological transformation of the layers of the package substrate in order to simplify the routing problem into a problem of connecting points on a circle with non-intersecting straight line segments. The circle, whi... » read more

Impact Modifiers and Compatibilizers for Versatile Epoxy-Based Adhesive Films with Curing and Deoxidizing Capabilities
By Technical Paper Link - 04 Feb, 2022 - Comments: 0

Abstract: "Epoxy resins with acidic compounds feature adhesion, robustness, and deoxidizing ability. In this study, hybrid adhesive films with deoxidizing and curing capabilities for semiconductor packaging were fabricated. The compatibilizing effects and mechanical properties were chiefly investigated by using various additive binders (thermoplastic amorphous polymers) and compatibilizing a... » read more

X-ray Imaging of Silicon Die Within Fully Packaged Semiconductor Devices
By Technical Paper Link - 21 Jan, 2022 - Comments: 0

Abstract: "X-ray diffraction imaging (XRDI) (topography) measurements of silicon die warpage within fully packaged commercial quad-flat no-lead devices are described. Using synchrotron radiation, it has been shown that the tilt of the lattice planes in the Analog Devices AD9253 die initially falls, but after 100 °C, it rises again. The twist across the die wafer falls linearly with an incre... » read more

Conceptualized Improvement on Transparent Glass Die for a Robust Manufacturing Process
By Technical Paper Link - 17 Jan, 2022 - Comments: 0

Abstract: "Glass die are one of the materials used by semiconductor plants during production of specialized quad-flat no-leads (QFN) products. With its transparent appearance and fragile characteristics, several challenges are encountered and analyzed to resolve unwanted issues and to have a robust process manufacturing. This paper will discuss a potential concept of process improvement on t... » read more

TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "Heterogeneous systems are commonly used today to sustain the historic benefits we have achieved through technology scaling. 2.5D integration technology provides a cost-effective solution for designing heterogeneous systems. The traditional physical design of a 2.5D heterogeneous system closely packs the chiplets to minimize wirelength, but this leads to a thermally-inefficient design... » read more

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and sol... » read more

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract: "More than Moore technologies can be supported by system-level diversification enabled by chiplet-based integrated systems within multichip modules (MCMs) and silicon interposer-based 2.5-D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at the ... » read more

Research on the Humidity Resistance Reliability of Different Packaging Structures
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "Packaging process is an indispensable part in the process of electronic components manufacturing, and its packaging quality directly affects the nominal power, reliability and other functions of the product in the subsequent application process. Through the research on the humidity resistance reliability of different packaging structures, C-Mount packaging structure, TO packaging str... » read more

A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials
By Technical Paper Link - 23 Dec, 2021 - Comments: 0

Abstract "The main motivation of this review is to study the evolution of first and second level of interconnect materials used in memory device semiconductor packaging. Evolutions of bonding wires from gold (Au) to silver (Ag) or copper (Cu) have been reported and studied in previous literatures for low-cost solution, but Au wire still gives highest rating in terms of the performance of tempe... » read more

Research on Wire Sweep of Integrated Circuit Packaging Based on Three-dimensional Flow Simulation
By Technical Paper Link - 31 Oct, 2021 - Comments: 0

Abstract: "Semiconductor manufacturing technology is becoming more and more rapidly. In the process of Integrated Circuit (IC) encapsulation, when wires contact each other, it will cause short circuit. Wire sweep has become the main factor affecting the reliability of the product. Therefore, it is a great challenge to master wire sweep in IC packaging process. This paper takes Low Profile Fi... » read more

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