category: Packaging

category: IoT, Security & Automotive

An Arrangement of Chiplets That Outperforms A Grid Arrangement (ETH Zurich / U. of Bologna)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A research paper titled "HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement" was published by researchers at ETH Zurich and University of Bologna. Abstract: "2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects ... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

Cost Characteristics of the 2.5D Chiplet-Based SiP System
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies" was published by researchers at UCSB, University of California, Santa Barbara. Abstract: "The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to ... » read more

Securing Heterogeneous Integration at the Chiplet, Interposer, and System-In-Package Levels (FICS-University of Florida)
By Technical Paper Link - 04 Aug, 2022 - Comments: 0

A new research paper titled "ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance" was published by researchers at the Florida Institute for Cybersecurity (FICS) Research, University of Florida. Abstract "The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Pa... » read more

Delay-based PUF for Chiplets to Verify System Integrity
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Know Time to Die – Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs" by researchers at University of Massachusetts, Amherst MA, Abstract (partial): "In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure un... » read more

Flip-Chip Integration of a GaSb Semiconductor Optical Amplifier with a Silicon Photonic Circuit
By Technical Paper Link - 01 Jul, 2022 - Comments: 0

New research paper titled "Hybrid silicon photonics DBR laser based on flip-chip integration of GaSb amplifiers and µm-scale SOI waveguides" by researchers at Tampere University (Finland). Abstract: "The development of integrated photonics experiences an unprecedented growth dynamic, owing to accelerated penetration to new applications. This leads to new requirements in terms of functional... » read more

Thermal Management Challenges and Requirements of 3 types of Microelectronic Devices
By Technical Paper Link - 20 Jun, 2022 - Comments: 0

New technical paper titled "A Review on Transient Thermal Management of Electronic Devices" from researchers at Indian Institute of Technology Bombay. Abstract "Much effort in the area of electronics thermal management has focused on developing cooling solutions that cater to steady-state operation. However, electronic devices are increasingly being used in applications involving time-varyi... » read more

Review of Bumpless Build Cube Using Wafer-on-Wafer & Chip-on-Wafer for Tera-Scale 3D Integration
By Technical Paper Link - 20 Jun, 2022 - Comments: 0

New research paper titled "Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)" from researchers at Tokyo Institute of Technology and others. Abstract "Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bum... » read more

Cu/SiO₂ Hybrid Bond Interconnects
By Technical Paper Link - 10 Jun, 2022 - Comments: 0

Technical paper titled "Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests" from researchers at TU Dresden and others. Abstract: "The focus of this study is a detailed characterization of hybrid Cu/SiO 2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding (or direct bond interconnect) is a technology of choice for fine pitch... » read more

Die-level Thinning and Integrating Route For Singulated MPW Chips Using Both Silicon Sensors and CMOS Devices
By Technical Paper Link - 30 Apr, 2022 - Comments: 0

Abstract "Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an el... » read more

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