category: Technical Papers

category: IoT, Security & Automotive

GPU Analysis Identifying Performance Bottlenecks That Cause Throughput Plateaus In Large-Batch Inference
By Technical Paper Link - 30 Mar, 2025 - Comments: 1

A new technical paper titled "Mind the Memory Gap: Unveiling GPU Bottlenecks in Large-Batch LLM Inference" was published by researchers at Barcelona Supercomputing Center, Universitat Politecnica de Catalunya, and IBM Research. Abstract "Large language models have been widely adopted across different tasks, but their auto-regressive generation nature often leads to inefficient resource util... » read more

Strategies For Reducing The Effective GaN/Diamond TBR
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications" was published by researchers at University of Bristol, Cardiff University and Akash Systems. Abstract "GaN high electron mobility transistors (HEMTs) on SiC substrates are the highest performing commercially available transistors for high-power, hi... » read more

Fully Digital Adaptive PMU-MCU System For Hybrid (Battery-Harvester) IoT Devices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "An Ultra-Low-Leakage Microcontroller with Configurable Power Management for Energy Harvesting IoT Devices" was published by researchers at Eindhoven University of Technology and Innatera Nanosystems. Abstract "This paper presents a power management unit (PMU) architecture designed for energy-harvesting IoT devices, integrating a dual-capacitor system, an ultra-... » read more

HW Implementation Of An ONN Coupled By A ReRAM Crossbar Array (IBM, TU Eindhoven)
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks" was published by researchers at IBM Research Europe and Eindhoven University of Technology. Abstract "We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. ... » read more

Experimental Characterization Results and State-of-the-Art Device-Level Studies of DRAM Read Disturbance
By Technical Paper Link - 25 Mar, 2025 - Comments: 1

A new technical paper titled "Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies" was published by researchers at ETH Zurich. Abstract "Modern DRAM is vulnerable to read disturbance (e.g., RowHammer and RowPress) that significantly undermines the robust operation of the system. Repeatedly opening and closing a DRAM ro... » read more

Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices
By Technical Paper Link - 25 Mar, 2025 - Comments: 0

A new technical paper titled "CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems" was published by researchers at UCLA, Duke University and Arizona State University. Abstract "With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to... » read more

Defect Analysis and Testing Framework For FOWLP Interconnects
By Technical Paper Link - 24 Mar, 2025 - Comments: 0

A new technical paper titled "Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging" was published by researchers at Arizona State University. Abstract "Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP fa... » read more

3D Photonic Integration For Ultra-Low-Energy, High-Bandwidth Interchip Data Links (Columbia et al.)
By Linda Christensen - 23 Mar, 2025 - Comments: 0

A new technical paper titled "Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links" was published by researchers at Columbia University, Cornell University, Air Force Research Laboratory Information Directorate and Dartmouth College. Abstract "Artificial intelligence (AI) hardware is positioned to unlock revolutionary computational abilities by ... » read more

Potential of AOS Memories As A High-Performance SRAM Substitute (Georgia Tech, U. of Virginia)
By Technical Paper Link - 21 Mar, 2025 - Comments: 0

A new technical paper titled "Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache" was published by researchers at Georgia Institute of Technology and University of Virginia. Abstract: "The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low oper... » read more

EFO Errors In The Wire-Bonding Semiconductor Packaging Process
By Technical Paper Link - 19 Mar, 2025 - Comments: 0

A new technical paper titled "A Comparative Study on Various Au Wire Rinse Compositions and Their Effects on the Electronic Flame-Off Errors of Wire-Bonding Semiconductor Package" was published by researchers at Hanbat National University, Seoul National University and Chungnam National University. The paper states: "In this study, we identify the origin of electronic flame-off (EFO) erro... » read more

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