category: Technical Papers

category: Auto, Security & Edge AI

Building Fixed HW Implementations of Neural Networks (Yale, Cornell et al.)
By Technical Paper Link - 29 May, 2026 - Comments: 0

Researchers from Yale University, Cornell University, Boston University, and NTT Research have published “Physical Foundation Models: Fixed hardware implementations of large-scale neural networks”. Abstract "Foundation models are deep neural networks (such as GPT-5, Gemini~3, and Opus~4) trained on large datasets that can perform diverse downstream tasks -- text and code generation, q... » read more

Characterization of GPU-based Inference for Reasoning-Centric LLMs (Micron, Argonne)
By Technical Paper Link - 26 May, 2026 - Comments: 0

Researchers from Micron Technology and Argonne National Laboratory have released “Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles”. Abstract “The transition from standard generative AI to reasoning-centric architectures, exemplified by models capable of extensive Chain-of-Thought (CoT) processing, marks a fundamental paradigm shift i... » read more

Detecting Defect-Induced Silent Data Corruptions in CPUs (Stanford, Google)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Stanford University and Google have published “ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions”. Abstract “Hyperscaler reports of silent data corruptions (SDCs)—presumed to be caused by silicon manufacturing defects—have motivated the development of functional tests for detecting defective CPUs and their use in h... » read more

Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung)
By Technical Paper Link - 25 May, 2026 - Comments: 0

A new technical paper, "Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory," was published by researchers from University of Seoul and Samsung Electronics. Abstract "This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggres... » read more

An Agent-Driven End-to-End HW-SW Co-Design Benchmark for Heterogeneous SoCs (Columbia, IBM)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Columbia University and IBM Research have released “HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip”. Abstract “Large language models (LLMs) are adopted for software and hardware design, yet these domains are still evaluated separately. Software benchmarks typically assume fixed hardware targets, while hardware be... » read more

Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Grenoble INP - UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, a... » read more

Improving GPU Energy Efficiency With Component-Level Power Management (AMD)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from AMD released “CompPow: A Case for Component-level GPU Power Management”. Abstract “The ever increasing demand for ML-driven intelligence in a wide spectrum of domains has led to ubiquity of GPUs. At the same time, GPUs are notorious for their power consumption needs and often dominate power allocation in a typical ML datacenter. While datacenter-level power opti... » read more

Large-scale, SRAM-based LLM Inference Deployment (Groq)
By Technical Paper Link - 21 May, 2026 - Comments: 0

A new technical paper, "SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving," was published by researchers at Nvidia, with work done while at Groq. Abstract "The proliferation of large language models (LLMs) demands inference systems with both low latency and high efficiency at scale. GPU-based serving relies on HBM for model weights and KV caches, creating a memory bandwidth b... » read more

Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)
By Technical Paper Link - 20 May, 2026 - Comments: 0

A new technical paper, "Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning," was published by researchers at USC and University of Wisconsin-Madison. Abstract "Reasoning LLMs produce thousands of chain-of-thought tokens whose KV cache must reside in scarce GPU HBM. The dominant response -- permanently evicting low-importance tokens -- is catastrophic for reasoni... » read more

A Deionized Water-Based Large-Scale Transfer Process For 2D Materials Grown on Sapphire (AMO, RWTH, Aixtron)
By Technical Paper Link - 18 May, 2026 - Comments: 0

A new technical paper, "Water-based, large-scale transfer of 2D materials grown on sapphire substrates," was published by researchers at AMO GmbH, RWTH Aachen University, and AIXTRON SE. Abstract "Two-dimensional materials (2DMs) hold significant potential for future electronics, as demonstrated by high-performing devices for sensing, optics, and electronics. However, scalable growth tech... » read more

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