Stacked Ferroelectric Memory Array Comprised Of Laterally Gated Ferroelectric Field-Effect Transistors


A technical paper titled “Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3  for stacked in-memory computing array” was published by researchers at Samsung Electronics and Sungkyunkwan University. Abstract: "In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfe... » read more

A Modelling Approach To Well-Known And Exotic 2D Materials For Next-Gen FETs


A technical paper titled “Field-Effect Transistors based on 2-D Materials: a Modeling Perspective” was published by researchers at ETH Zurich. Abstract: "Two-dimensional (2D) materials are particularly attractive to build the channel of next-generation field-effect transistors (FETs) with gate lengths below 10-15 nm. Because the 2D technology has not yet reached the same level of maturity... » read more

Benefits Of Using Wireless Communication Technologies In Power Electronics Systems Employing AGDs


A technical paper titled “Wireless Control of Active Gate Drivers for Silicon Carbide power MOSFETs” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract: "Active Gate Drivers (AGDs) enhance controllability and monitoring of switching devices, especially for fast switching Silicon Carbide (SiC) power Metal-Oxide-Semiconductor Field-Effect Transis... » read more

Progress In The Fabrication Of CMOS Devices Based On Stacked 2D TMD Nanoribbons (Intel)


A technical paper titled “Process integration and future outlook of 2D transistors” was published by researchers at Intel Corporation. Abstract: "The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the r... » read more

FeFET Multi-Level Cells For In-Memory Computing In 28nm


A technical paper titled “First demonstration of in-memory computing crossbar using multi-level Cell FeFET” was published by researchers at Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich. Abstract: "Advancements in AI led to the emergence of in-memory-computing architectures as a... » read more

Scalable And Compact Multi-Bit CAM Designs Using FeFETs


A technical paper titled “SEE-MCAM: Scalable Multi-bit FeFET Content Addressable Memories for Energy Efficient Associative Search” was published by researchers at Zhejiang University, China, Georgia Institute of Technology, University of California Irvine, Rochester Institute of Technology, University of Notre Dame, and Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of ... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs


A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Estimating the Embedded Gate Resistance to Reproduce SiC MOSFET Circuit Performance (ROHM)


A technical paper titled “Improved Scheme for Estimating the Embedded Gate Resistance to Reproduce SiC MOSFET Circuit Performance” was published by researchers at ROHM Company. Abstract: "The intrinsic gate resistance ( Rg_in) , which is a novel resistance factor embedded in transistors, was determined for silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFE... » read more

Noise Parameter Survey Of Millimeter Wave GaN HEMT Technologies


A technical paper titled “A Survey of GaN HEMT Technologies for Millimeter-Wave Low Noise Applications” was published by researchers at Wright-Patterson AFB, Teledyne Scientific, HRL Laboratories, BAE Systems, Pseudolithic, Northrop Grumman Corporation, and University of California Santa Barbara. "This article presents a set of measured benchmarks for the noise and gain performance of si... » read more

Integration Of Layered Semimetals With Conventional CMOS Platform


A technical paper titled “Layered semimetal electrodes for future heterogeneous electronics” was published by researchers at IIT Madras and Indian Institute of Science Education and Research. Abstract: "Integration of the emerging layered materials with the existing CMOS platform is a promising solution to enhance the performance and functionalities of the future CMOS based integrated cir... » read more

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