Securing The IoT


Semiconductor Engineering sat down to discuss whether the [getkc id="76" comment="Internet of Things"] will be secure enough, or whether it will create new security issues, with Sami Nassar, general manager of [getentity id="22499" comment="NXP Semiconductor"]; Oleg Logvinov, director for special assignments at [getentity id="22331" comment="STMicroelectronics"]; and Lawrence Loh, application e... » read more

Memory Directions Uncertain


Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Litho Options Sparse After 10nm


Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in [getkc id="80" comment="lithography"], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—[gettech id="... » read more

Design Rules Explode At New Nodes


Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

ATE Market Gets More Crowded


Over the years, the automatic test equipment (ATE) industry has undergone a dramatic shakeout. In fact, the ATE industry has shrunk from about a dozen major vendors several years ago to just three sizable companies today. There is also a smattering of smaller ATE players in the market. In other words, the big ATE vendors became bigger and the mid-sized players were gobbled up. The consol... » read more

The Key To DSA


The block co-polymer most commonly used in directed self-assembly research ([gettech id="31046" t_name="DSA"]), PS-b-PMMA (poly(styrene-block-methyl methacrylate) is an excellent choice because the two component monomers have similar surface energies. The exposed top surface of the film helps to stabilize the segregated domains, making it relatively easy to achieve the lamellar line-and-space p... » read more

Challenges Mount For EUV Masks


Five years ago, Intel urged the industry to invest millions of dollars in the photomask infrastructure to help enable extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography. At the time, there were noticeable gaps in EUV, namely defect-free masks and inspection tools. To date, however, Intel’s call to action has produced mixed results. The photomask industry is making progr... » read more

Executive Insight: Aki Fujimura


Semiconductor Engineering sat down to discuss photomask technology and lithography trends with Aki Fujimura, chairman and chief executive of D2S. SE: What are the big challenges that keep you awake at night? Fujimura: Mask technology, and the investments in the mask industry, are increasingly important. But so far, the investment dollars that the community is willing to spend on it isn’... » read more

High-Level Gaps Emerge


Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow with Bernard Murphy, CTO at [getentity id="22026" e_name="Atrenta"]; Leah Clark, associate technical director for digital video technology at Broadcom; Phil Bishop, vice president of the system level design system & verification group at [getentity id="22032" e_name="Cadence"]; and Jon McDon... » read more

One-On-One: Mike Muller


SE: What happens with memory, where access is more localized? Muller: Hybrid memory cube is one approach. HBM is another. ARM is chairing an IEEE standards group for a next-gen memory interface to make sure we build memories that fit mobile as well as networking and classic servers. Whereas in the past, memories were driven from the performance, we need to make the power scales with the band... » read more

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