Re-shoring And Rebuilding The IC Supply Chain


Raj Jammy, chief technologist at MITRE Engenuity and executive director of the Semiconductor Alliance, sat down with Semiconductor Engineering to talk about changes in the supply chain, where and how to leverage different capabilities, and why advanced packaging and manufacturing are so critical to economic security. SE: The global supply chain for semiconductors appears to be splintering. W... » read more

How To Build Resilience Into Chips


Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

Taming Corner Explosion In Complex Chips


There is a tenuous balance between the number of corners a design team must consider, the cost of analysis, and the margins they insert to deal with them, but that tradeoff is becoming a lot more difficult. If too many corners of a chip are explored, it might never see production. If not enough corners are explored, it could reduce yield. And if too much margin is added, the device may not be c... » read more

Leveraging Chip Data To Improve Productivity


The semiconductor ecosystem is scrambling to use data more effectively in order to increase the productivity of design teams, improve yield in the fab, and ultimately increase reliability of systems in the field. Data collection, analysis, and utilization is at the center of all these efforts and more. Data can be collected at every point in the design-through-manufacturing flow and into the f... » read more

Dealing With Performance Bottlenecks In SoCs


A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

Safety, Security, And Reliability Of AI In Autos


Experts at the Table: Semiconductor Engineering sat down to talk about security, aging, and safety in automotive AI systems, with Geoff Tate, CEO of Flex Logix; Veerbhan Kheterpal, CEO of Quadric; Steve Teig, CEO of Perceive; and Kurt Busch, CEO of Syntiant. What follows are excerpts of that conversation, which was held in front of a live audience at DesignCon. Part one of this discussion is he... » read more

Process Innovations Enabling Next-Gen SoCs and Memories


Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher th... » read more

Managing Thermal-Induced Stress In Chips


At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Devices And Transistors For The Next 75 Years


The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

2D Semiconductor Materials Creep Toward Manufacturing


As transistors scale down, they need thinner channels to achieve adequate channel control. In silicon, though, surface roughness scattering degrades mobility, limiting the ultimate channel thickness to about 3nm. Two-dimensional transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are attractive in part because they avoid this limitation. With no out-of-plane dangling bonds and at... » read more

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