The March Toward Chiplets


The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

3D-IC Reliability Degrades With Increasing Temperature


The reliability of 3D-IC designs is dependent upon the ability of engineering teams to control heat, which can significantly degrade performance and accelerate circuit aging. While heat has been problematic in semiconductor design since at least 28nm, it is much more challenging to deal with inside a 3D package, where electromigration can spread to multiple chips on multiple levels. “Be... » read more

Variability Becoming More Problematic, More Diverse


Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

IC Stresses Affect Reliability At Advanced Nodes


Thermal-induced stress is now one of the leading causes of transistor failures, and it is becoming a top focus for chipmakers as more and different kinds of chips and materials are packaged together for safety- and mission-critical applications. The causes of stress are numerous. In heterogeneous packages, it can stem from multiple components composed of different materials. “These materia... » read more

Challenges With Adaptive Control


Historically, the performance and power consumption of a system was controlled by what could be done at design time, but chips today are becoming a lot more adaptive. This has become a necessity for cutting edge nodes, but also provides a lot of additional benefits at the expense of greater complexity and verification challenges. Design margins are a tradeoff between performance and yield. C... » read more

Improving Chip Efficiency, Reliability, And Adaptability


Peter Schneider, director of Fraunhofer Institute for Integrated Circuits' Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about new models and approaches for ensuring the integrity and responsiveness of systems, and how this can be done within a given power budget and at various speeds. What follows are excerpts of that conversation. SE: Where are y... » read more

Startup Funding: November 2022


November was a month for mega-rounds, with ten companies receiving investments of at least $100 million. One of those is a startup providing connectivity solutions for data centers and enabling use of the memory pooling functionality in the latest update to the CXL standard. Two quantum computer startups were part of the $100M+ club this month — one using very cold atoms to take on not only q... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes


Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Adopting Predictive Maintenance On Fab Tools


Predictive maintenance, based on more and better sensor data from semiconductor manufacturing equipment, can reduce downtime in the fab and ultimately cut costs compared with regularly scheduled maintenance. But implementing this approach is non-trivial, and it can be disruptive to well-honed processes and flows. Not performing maintenance quickly enough can result in damage to wafers or the... » read more

High Voltage Testing Races Ahead


Voltage requirements are increasing, especially for the EV market. Even devices that might be considered relatively low voltage, such as display drivers, are now pushing past established baselines. While working with high voltages is nothing new — many engineers can recall yellow caution tape in their workplaces — the sheer number and variety of new requirements have made testing at high... » read more

← Older posts Newer posts →