category: Power Awareness

category: IoT, Security & Automotive

The Pain of UPF/CPF
By Ann Mutschler - 10 Feb, 2011 - Comments: 0

Without entering into a debate on the merits of the UPF and CPF, there is a very real and valid concern that designers have today regarding these power intent formats. According to Krishna Balachandran, director of product marketing for low-power verification products at Synopsys, design teams are questioning the validity/correctness of the resulting code. Because they are learning these ... » read more

The Challenge Of Packaging
By Ann Mutschler - 13 Jan, 2011 - Comments: 0

Semiconductor packaging isn’t a sexy subject, and it’s one that’s been largely overlooked by the design community. Until now, that is. I recently spoke with Brad Griffin at Cadence, who stressed that managing the power through packages even on a single die is still one of the most challenging things engineers must navigate. “As people integrate more technology into a single chip o... » read more

Silence Is Golden
By Ann Mutschler - 01 Dec, 2010 - Comments: 0

As the industry continues to march along building devices with ever-increasing battery life, it is necessary to migrate to the latest and greatest process nodes, which as we all know are smaller and use lower voltages. However, any noise in the system—whether it was there before or you start to use something like USB 3.0 or SATA or something else—is actually going to increase the number of ... » read more

Making Power Delivery Networks Better
By Ann Mutschler - 04 Nov, 2010 - Comments: 0

Careful design of power delivery networks can make the difference in whether a chip manages power effectively or fails completely. This impact of cost and other factors in the design process has not gone unnoticed. Aveek Sarkar, vice president of customer support and product engineering at Apache Design Solutions, pointed to the iPhone as an example, where 50% or more of the bill of material... » read more

Connecting IP Blocks
By Ann Mutschler - 07 Oct, 2010 - Comments: 0

Is there a standard way to hook up specifically low-power IP blocks today? For all intents and purposes, no. Before even talking about IP interoperability in terms of power, Philippe Magarshack, general manager of central CAD and design solutions at STMicroelectronics asserted those IPs must be hooked up correctly functionally and in a productive and safe way. He said ST is forging ahead ... » read more

Burn, Baby, Burn
By Ann Mutschler - 09 Sep, 2010 - Comments: 0

Obviously, software burns power on mobile devices, but exactly how? I found out recently, thanks to Pete Hardee, director of solutions marketing at Cadence Design Systems. Essentially, Hardee said, there are four ways that software burns power, following in order from most to least. First, depending on the mode, various peripherals are on and off and the big one for a smartphone is the LC... » read more

iPhone Has The Power Blues
By Ann Mutschler - 12 Aug, 2010 - Comments: 0

Why do some apps on the iPhone seem to draw more on the battery than others? Is it a matter of power-aware software applications, or is it a hardware issue? Maybe it is a combination of both. I suspect it is due to the intricacies of hardware/software design and verification. I’ve been mulling this over while researching my two articles for this month’s issue of Low-Power Engineering... » read more

Power Makes IP Integration More Fun
By Ann Mutschler - 08 Jul, 2010 - Comments: 0

Remember the good old days at 130nm when it was easy to combine IP blocks on an SoC? All kidding aside, because obviously IP integration has always had its challenges, designers are experiencing new pain as process, voltage and temperature wreak havoc in bringing everything together and making sure it operates correctly, meeting all power requirements. As I discovered, whether IP comes from ... » read more

Giant Steps—Backward
By Ann Mutschler - 10 Jun, 2010 - Comments: 0

With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

Optimizing Physical IP For Applications And Processors
By Ann Mutschler - 13 May, 2010 - Comments: 0

What will the next challenges be for chip designers as the industry moves toward 28nm high-k metal gate manufacturing technology? One thing is for sure, power management may get even more painful without new innovations to handle the characteristics of 28nm. Optimization is definitely the approach that keeps creeping up as I talk with folks in the industry with ARM specifically mentioning ap... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy