category: Whitepapers

category: IoT, Security & Automotive

Advanced Power And Performance Optimization For Multicore SoCs
By Synopsys - 11 Feb, 2015 - Comments: 0

The Multicore Optimization (MCO) technology in Synopsys Platform Architect provides an environment for early exploration and optimization of complex Multicore SoC (MP-SoC) platforms. It allows quantitative analysis of performance and power metrics to avoid SoC market failure due to underperforming or power hungry architectures. To read more, click here. » read more

Leveraging Physically Aware Design-For-Test To Improve Area, Power, And Timing
By Cadence - 11 Feb, 2015 - Comments: 0

Increased pressures on design teams to deliver faster, smaller devices in less time has required EDA companies to develop an integrated methodology to incorporate physical design information during DFT synthesis. This solution must consider the placeable area (or size) of the circuit as well as routing blockages and hard macro placement locations. It must also be able to both model the wiring i... » read more

Optimizing Emulator Utilization
By Mentor, a Siemens Business - 11 Feb, 2015 - Comments: 0

Russ Klein describes how Codelink, a Mentor Graphics trace-based debug tool, gives software developers a traditional software debug view from a unique processor trace, enabling them to increase emulator utilization and enjoy a more productive debug experience. Codelink allows for software debug earlier in the design cycle, as it makes it possible to use the emulator without having debug circuit... » read more

CoreSight SoC
By Arm - 05 Feb, 2015 - Comments: 0

To address the challenge of increasing development cost and complexity faced by the semiconductor industry, SoC designers need to think ahead and provide the right hardware platform to help software developers create optimized software in a timely manner. The goal of this paper is to show, through high level steps, how to create a custom debug and trace subsystem for a design quickly and easily... » read more

Round-Trip Engineering Key To AUTOSAR-based Development
By Mentor, a Siemens Business - 05 Feb, 2015 - Comments: 0

This paper discusses how round-trip engineering can be used as an iterative development process and describes interoperability between tools from Mentor and MathWorks. Model-based design has become an important component in vehicle manufacturer and supplier development processes. Electronic control units are complex in terms of functionality, connectivity, and variants; therefore automotive ... » read more

A Complete Analog Design Flow For Verification Planning And Requirement Tracking
By Mentor, a Siemens Business - 28 Jan, 2015 - Comments: 0

Verifying designs to meet all specifications across all process corners has become an intractable problem from the perspective of debugging, managing, tracking, and meeting verification goals. Implementing a CDV methodology for analog designs can evolve analog design and verification to a standard process-based method that can be tracked and its progress measured. This paper aims to extend comm... » read more

Solving The ASIC Prototype Partition Problem With Synopsys ProtoCompiler
By Synopsys - 28 Jan, 2015 - Comments: 0

When developing a multi-FPGA prototype of an ASIC or SoC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules should be assigned to each FPGA; where and how many cables connect the FPGAs; and how to squeeze all the signals into those cables. All these decisions need to result in the fastest possible prototype that... » read more

EDT Test Points
By Mentor, a Siemens Business - 22 Jan, 2015 - Comments: 0

Embedded test compression was commercially introduced over a decade ago and has scaled to well beyond the 100X range envisioned when it was first introduced. However, growing gate counts enabled by new technology nodes as well as new fault models targeting defects within standard cells are driving the need for even greater compression levels. This paper describes an exciting new technology, cal... » read more

Developing High-Performance, Low-Power Audio/Voice Subsystems Using Customizable DSP Blocks And Audio Interface IP
By Cadence - 14 Jan, 2015 - Comments: 0

As applications such as mobile gaming and voice triggering grow in popularity, audio/voice subsystems are becoming more important in many mobile system-on-chip (SoC) designs. Subsystem requirements have evolved to address multiple demands: high-performance, high-resolution audio stream processing, and always-on, low-power voice trigger and recognition. This white paper describes how customizabl... » read more

Designing the Right Architecture
By Synopsys - 14 Jan, 2015 - Comments: 0

Designing the right architecture of a multi-processor SoC for today's sophisticated electronic products is a challenging task. The most critical element for meeting the performance requirements of the entire system is the interconnect and memory architecture. These SoC infrastructure IP components are highly configurable and need to be customized to the communication needs of all the other modu... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy