category: Videos

category: IoT, Security & Automotive

Globally Asynchronous, Locally Synchronous Clocks
By Ed Sperling - 04 Nov, 2024 - Comments: 0

Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes ... » read more

Working With Chiplets
By Ed Sperling - 02 Oct, 2024 - Comments: 0

The usual method of migrating to the next process node to cram more features onto a piece of silicon no longer works. It's too expensive, and too limited for most applications. The path forward is now heterogeneous chiplets targeted at specific markets, and while logic will continue to scale, other features are being separated out into chiplets developed using different process technologies. Th... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Changes In Formal Verification
By Ed Sperling - 11 Jul, 2024 - Comments: 0

For the better part of two decades, formal verification was considered too difficult to use in many designs and too slow for anything but narrow bug hunting. Much has changed recently. Ashish Darbari, CEO of Axiomise, explains why formal is now essential for finding deadlocks, security holes, and Xprop issues in mission-critical, safety-critical, and AI designs, and how that will apply to chipl... » read more

Promises And Pitfalls Of SoC Restructuring
By Ed Sperling - 12 Jun, 2024 - Comments: 0

As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, explains why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interface... » read more

Electromigration And IR Drop At Advanced Nodes
By Ed Sperling - 22 May, 2024 - Comments: 0

Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil... » read more

Challenges In RISC-V Verification
By Ed Sperling - 02 Apr, 2024 - Comments: 0

Designing a single-core RISC-V processor is relatively easy, but verifying it and debugging it is a different story. And it all becomes more complicated when multiple cores are involved, and when those cores need to be cache-coherent. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about using assertions and formal verification technology to find bugs and prove coherency i... » read more

Cache Coherency In Heterogeneous Systems
By Ed Sperling - 01 Apr, 2024 - Comments: 0

Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst... » read more

Integration Challenges For RISC-V Designs
By Ed Sperling - 27 Feb, 2024 - Comments: 0

One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at ... » read more

Densification Of RF Designs
By Ann Mutschler - 20 Dec, 2023 - Comments: 0

It’s challenging enough to deal with wireless signals at the 5G and 6G frequencies. But with increased density in chips crammed into smaller packages, higher power, beam forming, and MIMO, design requirements are very different than in the past. Simple parasitic extraction no longer is sufficient. Daren McClearnon, product manager for RF and microwave simulation at Keysight, talks about the n... » read more

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