Next-Gen Design Challenges


As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Network Interface Card Evolution


Longer chip lifetimes, more data to process and move, and a slowdown in the rate of processor improvements has created a series of constantly shifting bottlenecks. Kartik Srinivasan, director of data center marketing at Xilinx, looks at one of those bottlenecks, the network interface card, why continuous enhancements and changes will be required, and how to extend the life of NICs as the networ... » read more

Customized Micro-Benchmarks For HW/SW Performance


Raw performance used to be the main focus of benchmarks, but they may have outlived their usefulness for many applications. Dana McCarty, vice president of sales and marketing for AI Inference Products at Flex Logix, talks about why companies need to develop and utilize their own specific models to accurately gauge hardware and software performance, which can be slowed by bottlenecks in I/O and... » read more

Changing The Rules For Chip Scaling


Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

Security In FPGAs And SoCs


Chip security is becoming a bigger problem across different markets, with different emerging standards and more sophisticated attacks. Jason Moore, senior director of engineering at Xilinx, talks with Semiconductor Engineering about current and future threats and what can be done about them. » read more

Securing ICs With Information Flow Analysis


Following the data has new meaning when it comes to security. Alric Althoff, senior hardware security engineer at Tortuga Logic, talks about tracking the flow of data through a hardware design over time, including what happens with roots of trust, how this works with existing tools and methodologies, and what to think about when tracing potential security risks. » read more

Better Quality RTL


How do you measure the quality of RTL? Philippe Luc, director of verification at Codasip, talks about identifying bugs, improving the overall quality of the verification, what happens when different blocks are used in a design, and how to improve efficiency in the verification process. » read more

Data Overload In The Data Center


Dealing with increasing volumes of data inside of data centers requires an understanding of architectures, the flow of data between memory and processors, bandwidth, cache coherency and new memory types and interfaces. Gary Ruggles, senior product marketing manager at Synopsys, talks about how these systems are being revamped to improve performance and reduce power. » read more

IP Safe Enough To Use In Cars


IP that is used for functional safety needs to respond to events that can happen, whether those are planned or random. Jody Defazio, vice president of IP quality and functional safety at Synopsys, talks with Semiconductor Engineering about ASIL compliance, what the different levels mean, and the impact of using chips developed at the most advanced process nodes in automotive applications. » read more

Silicon Lifecycle Management


How do you track, measure and ensure reliability over the lifetime of a chip, regardless of how or where it is used? Steve Pateras, senior director of marketing for test products at Synopsys, drills down into the impact of hardware-software co-design, over-the-air updates, the expected lifetime of designs, and how the various monitors and sensors are used to track environmental, structural and ... » read more

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