Tech Talk: Neural Networks


Megha Daga, senior technical marketing manager at Cadence, talks with Semiconductor Engineering about convolutional neural networks, including the bandwidth and compute challenges associated with them. » read more

Tech Talk: System In Package


ASE fellow and senior technical advisor William Chen talks about advanced packaging options and why they are now so important. » read more

Tech Talk: Cryogenic DRAM


Rambus Chief Scientist Craig Hampel talks with Semiconductor Engineering about quantum computing and the power/performance benefits of running DRAM at extremely low temperatures. https://youtu.be/3qu2mspJeM0 » read more

Tech Talk: eFPGA Acceleration


Achronix's Kent Orthner talks about when and why to use embedded FPGAs, and how they co-exist with—and compare to—other processing elements. [youtube vid=TXeIOmo7O9o] » read more

Biz Talk: ASICs


eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Tech Talk: Ethernet


George Hervey, principal architect at Marvell, talks about the power efficiency of networking in the enterprise and how much money can be saved by rightsizing Ethernet equipment. [youtube vid=PxDR94UOFaM]     Related Stories Executive Insight: Sehat Sutardja Marvell’s CEO talks about the rising cost of design and why new packaging approaches are essential. » read more

Tech Talk: Extending DRAM


Bruce Bateman, senior principal engineer at Kilopass, talks about how to extend the life of DRAM and how to work with smaller, denser memory.   Related Stories Executive Insight: Charlie Cheng Kilopass’ CEO talks about how to cut the capacitor in DRAM and why that’s important in the data center. » read more

Tech Talk: Timing Closure


Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade.   Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

Tech Talk: FD-SOI vs. FinFET


Jamie Schaeffer, 22FDX program director at GlobalFoundries, talks about the future of FD-SOI, what the tradeoffs are in performance, power and cost compared with finFETs, how many mask layers and patterning steps are required for each, and when 12nm FD-SOI will be introduced. Related Stories To 7nm And Beyond GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economi... » read more

Tech Talk: Earlier Software


Malte Doerper, senior manager of product management at Synopsys, talks about the big "shift left" for software, where the problems crop up, and how to save as much as a year of development time with automation and better methodologies.   Related Stories Bridging Hardware And Software The need for concurrent hardware-software design and verification is increasing, but are engine... » read more

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