Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters.
https://youtu.be/HwRe9DHLfmg
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Marvell's Sathya Subramanian talks with Semiconductor Engineering about the new 802.11ax wireless standard, how it will work with 5G and existing networks, and how to set up an integrated solution to reduce bottlenecks in the home and in the enterprise.
https://youtu.be/KZP59qw6j4Y » read more
Flex Logix’s Cheng Wang talks about which types of chips work best for neural networks, AI and machine learning.
https://youtu.be/k7OdP7B10o8 » read more
Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design.
https://youtu.be/AOWh4wjw-ps » read more
Brewer Science’s Dominic Miranda digs into printed electronics, why they’re becoming so important, what materials should be used, and how they can be targeted for specific applications in sensors and edge devices.
https://youtu.be/tN2goxrDCqA » read more
Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process.
https://youtu.be/Jq4XUKnniB4 » read more
eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power.
https://youtu.be/E-CU8TLvjjc » read more
OneSpin Solutions’ Muhammed Haque Khan, product specialist for synthesis verification, digs into equivalence checking in FPGA designs and what can go wrong with FPGA designs.
https://youtu.be/RFlP2Z_-Yqs » read more
Synopsys’ Manmeet Walia talks examines the impact of machine-to-machine traffic and why that requires some fundamental changes in networking architectures. Two key issues that need to be addressed are scalability and latency, which require new networking architectures.
https://youtu.be/2RIQt3QVPtE » read more
Jamie Shaeffer, senior director of product line management at GlobalFoundries, talks about how FD-SOI compares with bulk technologies, where it will be used and why, and future stacking options.
https://youtu.be/2i7GJRxcNRs » read more
S. Korea goes All In on AI; new Dresden power fab; Intel expansion; GM secures memory supply; AI power management funding; mature-node foundry capacity; 300mm fab equipment; McKinsey's map of strategic IC supply; security threats; AI burnout.
Intel's expansion; Cadence AI super agent for PCB, advanced packaging; photonics fab wars; earlier Yongin fab; German funding; new CHIPS Act award; HBM standard; Quadric funding; AMS acquisition; earnings; Rapidus teams up.
Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnect protocols, requiring design tradeoffs and extra reliability measures.
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.
Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency.
Processor architectures are evolving faster than ever, but they still lag the pace of AI development. Chip architects must predict what will be required tomorrow in designs today.
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