Coventor’s CTO digs into multi-patterning, new transistor types, and the biggest problems for device scaling.
David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types.
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This is just one version of SAQP that is presented. There is another way to reach the 36 nm pitch, which is just another form of SADP. https://en.wikipedia.org/wiki/File:7nm_BEOL_Double_Patterning.png The vias can also be just LELE, because of the gate pitch being looser.
The Wikipedia article on multiple patterning is pretty good: https://en.wikipedia.org/wiki/Multiple_patterning
It also describes alternatives to SAQP such as SADP where spacer is dielectric (SID). 7nm pitches may only need double patterning: https://en.wikipedia.org/wiki/File:7nm_BEOL_Double_Patterning.png
Also, cut redistribution can eliminate the mask number problem: https://en.wikipedia.org/wiki/File:Cut_Redistribution.png