Tech Talk: 7nm Litho

Coventor’s CTO digs into multi-patterning, new transistor types, and the biggest problems for device scaling.


David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types.

Related Stories
Inside Next-Gen Transistors
Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China.
Faster Time To Yield
Coventor’s CEO talks about how to get chips through manufacturing more quickly.


memister says:

This is just one version of SAQP that is presented. There is another way to reach the 36 nm pitch, which is just another form of SADP. The vias can also be just LELE, because of the gate pitch being looser.

memister says:

The Wikipedia article on multiple patterning is pretty good:

It also describes alternatives to SAQP such as SADP where spacer is dielectric (SID). 7nm pitches may only need double patterning:

Also, cut redistribution can eliminate the mask number problem:

Leave a Reply

(Note: This name will be displayed publicly)