Why Matter 1.0 Really Matters


Incompatibilities of consumer devices inside the home are frustrating for consumers and a security risk. Skip Ashton, distinguished engineer at Infineon, talks about how the Matter 1.0 standard will fuse together different ecosystems from companies such as Apple, Google, and Amazon, how it will be applied to existing devices, what’s included and missing from the standard today, and how it can... » read more

Managing IP In Heterogeneous Designs


Increasing complexity and heterogeneity is creating huge challenges for tracking different versions of IP over the lifetime of chips. Pedro Pires, applications engineer at ClioSoft, talks about the implications of IP reuse in a complex, multi-IP context, including how different standards and database formats can affect IP tracking and why an interoperability layer is essential to tracking IP an... » read more

Automated Optical Inspection


Building good automated models for inspection require more data to be collected, both good and bad. Vijay Thangamariappan, R&D engineer at Advantest, explains how to develop models for automating optical inspection, using a multi-thousand pin socket as an example for how machine learning has helped reduce the return rate due to defects from 2% down to zero. He also explains how to achieve t... » read more

Testing 2.5D And 3D-ICs


Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

Why Changes In Computing Are Driving Changes In Photomasks


Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

HBM3 In The Data Center


Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

Simplifying AI Edge Deployment


Barrie Mullins, vice president of product at Flex Logix, explains how a programmable accelerator chip can simplify semiconductor design at the edge, where chips need to be high performance as well as low power, yet developing everything from scratch is too expensive and time-consuming. Programmability allows these systems to stay current with changes in algorithms, which can affect everything f... » read more

Using eFPGAs For Security


Andy Jaros, vice president at Flex Logix, talks about the use of eFPGAs to keep pace with security risks over longer chip lifetimes, how configurable RTL can help, and why systems companies are altering the playing field for FPGAs. » read more

Quantum Computing


Sebastian Luber, senior director of technology and innovation at Infineon Technologies, talks about the growing interest in quantum computers, what’s still missing to make this technology more relevant, and how to improve the lifespan and accuracy of qubits. » read more

Boosting Data Management System Performance


Marios Karatzias, application engineer at ClioSoft, talks with Semiconductor Engineering about the increasing use and re-use of IP in designs, how to best keep track of that IP, and how to optimize the performance of the data management system to deal with IP in heterogeneous chips. This is particularly important in automotive and industrial applications, where a specific version of IP may have... » read more

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