category: Videos

category: Auto, Security & Edge AI

PCIe Over Optics
By Ed Sperling - 03 Feb, 2025 - Comments: 0

Moving data through a chip or package, and between packages and systems, is becoming a much bigger challenge as the volume of data continues to explode, and as more compute resources are deployed to work on data-intensive problems such as training AI algorithms or running long and complex simulations. There is more data to process in more places, more levels of data storage and access, and any ... » read more

The Road To Super Chips
By Ed Sperling - 27 Jan, 2025 - Comments: 0

Reticle size limitations are forcing chip design teams to look beyond a single SoC or processor in order to achieve orders of magnitude improvements in processing that are required for AI. But moving data between more processing elements adds a whole new set of challenges that need to be addressed at multiple levels. Steve Woo, distinguished inventor and fellow at Rambus, examines the benefits ... » read more

Livelocks And Deadlocks In NoCs
By Ed Sperling - 22 Jan, 2025 - Comments: 0

Devices that are stuck in a specific state, or which appear to be making progress even though they are not, are common problems in complex systems. Processing elements need to fetch data they don't have from routers may be frozen out by other processors, a problem that is exacerbated by common bus protocols. Ashish Darbari, CEO of Axiomise, talks about how to identify potential bottlenecks, why... » read more

Distributed Voltage And Frequency Scaling Gaining Traction
By Ed Sperling - 16 Dec, 2024 - Comments: 0

DVFS has been used in smart phones for more than a decade as a way of trading off power and performance when both are constrained, but much of the semiconductor industry has avoided this technique because it's too difficult to work with. That's starting to change as processing demands increase, driven by the rollout of AI everywhere and an increase in the number of features in advanced packages... » read more

Speeding Up Acoustic Wafer Inspection
By Ed Sperling - 09 Dec, 2024 - Comments: 0

Higher density and more vertical layers require higher-resolution inspection. In the past that generally resulted in longer scan times, which can slow throughput in the fab or assembly house. Bryan Schackmuth, senior product line manager at Nordson Test & Inspection, explains how rotational scanning using acoustic wafer inspection can speed up inspection time by a factor of eight, why it is... » read more

The Evolution of HBM
By Ed Sperling - 04 Dec, 2024 - Comments: 0

High-bandwidth memory originally was conceived as a way to increase capacity in memory attached to a 2.5D package. It has since become a staple for all high-performance computing, in some cases replacing SRAM for L3 cache. Archana Cheruliyil, senior product marketing manager at Alphawave Semi, talks about how and where HBM is used today, how it will be used in the future, why it is essential fo... » read more

Using Formal For RISC-V Security
By Ed Sperling - 19 Nov, 2024 - Comments: 0

Finding and closing up security holes is becoming more important as chips are used in safety- and mission-critical applications, but it's increasingly important for chips designed for much less costly devices, where the selling price typically doesn't warrant a significant investment in security. The problem is these devices are connected to some of the same networks, and any access points for ... » read more

Scaling Performance In AI Systems
By Ed Sperling - 11 Nov, 2024 - Comments: 0

Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

Globally Asynchronous, Locally Synchronous Clocks
By Ed Sperling - 04 Nov, 2024 - Comments: 0

Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes ... » read more

Working With Chiplets
By Ed Sperling - 02 Oct, 2024 - Comments: 0

The usual method of migrating to the next process node to cram more features onto a piece of silicon no longer works. It's too expensive, and too limited for most applications. The path forward is now heterogeneous chiplets targeted at specific markets, and while logic will continue to scale, other features are being separated out into chiplets developed using different process technologies. Th... » read more

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