CDNLive 2019: The Verification Ecosystem Is Growing Stronger And Stronger

Ecosystems are not only fascinating when it comes to processors like Arm, MIPS, x86, and RISC-V (as I have written before) or for semiconductor technologies like TSMC, GLOBALFOUNDRIES, and Samsung; they are key for success in verification as well. CDNLive Silicon Valley was, again, a great example of the verification ecosystem in action. It showcased the different engines verification tools run on—simulation on x86- and Arm-based servers, on-premise and in the cloud, emulation and prototyping—but also showcased IP enablement for processor and design IP and partner tools like job schedulers and cloud management for verification. The verification ecosystem is growing stronger and stronger!

I have blogged about the “Verification Village” before, outlining the ecosystem around test equipment from Teledyne Lecroy, Rohde & Schwartz, the Keysight Business Ixia, and National Instruments. Then, in my blog on last year’s CDNLive Silicon Valley, I talked about user presentations from NVIDIA and MicroSemi combining emulation and prototyping; on the ecosystem side, about National Instruments’ “Design to Test” and Keysight Ixia’s “Ethernet Testing,” as well as Samsung using Altair’s Hero tool from their acquisition of Run Time Design Automation for job scheduling in Palladium, maximizing the utilization of the emulator.

This year’s CDNLive Silicon Valley showcased the use of the verification ecosystem equally strong, if not stronger.

Let’s start with the cloud aspects of the verification ecosystem. An ecosystem is where users run their verification jobs. X86- and Arm-based servers run in the cloud, and Cadence is partnering with AWS, Azure, and Google Cloud to allow access to our software-based tool suites. We also co-locate billions of gates of Palladium capacity to make emulation cloud-accessible to users as well.

As users, Ampere and Wright Patterson’s Air Force Research Laboratories (AFRL) talked about their cloud usage of emulation. The title of Ampere’s presentation, “Achieving quick and painless emulation of next-generation CPUs for cloud and edge servers using the Palladium Cloud Solution,” pretty much sums it up. In their presentation, Ampere mentions some of the Palladium advantages like deterministic compile performance, fast compile turns for early design phases where RTL is regularly changing and the stability of hardware while running industry benchmarks that span weeks of runtime. Key from a cloud perspective, was that there were no visible network latency issues as hardware hosted in North America.

For AFRL, the cloud, as described in “Nimbis TSS Cloud Execution Environment,” it was all about having a ready-to-use infrastructure for researchers rather than having to deal with multiple configurations to setup of licenses, tool installs, and libraries, etc. They estimate about 400 users with about 1/3 of them active. One key point is the preservation of data. The ability to have instances that can live in the cloud indefinitely to ease redeployment—even after a researcher moved off to other projects—augments simply archiving tar-balls that were already typical. Having instances preserved in the cloud makes the transition much easier for new users who, in the past, didn’t know the environment.

On the ecosystem partner side, Methodics was talking about “Creating a Seamless Cloud-Bursting Environment for Verification,” focusing on efficiently managing regressions in the cloud and to control how tests are executed in the cloud with proper version dependencies and OS versions, with all design files being available.

The next ecosystem area centers around processor and design IP. At last year’s CDNLive, we were talking with Arm about how to integrate design IP like PCIe into server chips, enabling a lively ecosystem from Arm and Cadence IP to chip makers like Marvell and system integrators like HPE. This year’s CDNLive saw the Tensilica group at Cadence talk about their DNA100 processors for AI and how they verified it on Palladium in “Validation of Tensilica DNA 100 IP’s AI Hardware Accelerator by Running Popular NNs on Hardware Emulation Platform.” Together with Arm, we presented, “Optimizing Hardware/Software Development for Arm-Based Embedded Designs.” I am looking forward to CDNLive EMEA—just two weeks away, happening in Munich May 6^th to 8^th—where we will have Imperas present on Arm, MIPS and RISC-V integration as well.

In the ecosystem area of test interfaces, Keysight Ixia presented on the latest developments of how to allow Ethernet testing with physical and virtual connections to Palladium in “Virtual Ethernet Design Verification with IxVerify and Palladium Platform.” Just two weeks after CDNLive Silicon Valley, at DVCON China, we also presented on testing for the 5G market, involving Keysight, Rohde & Schwartz and Anritsu.

Last but not least, software development, debug, and security/safety are additional ecosystem areas for verification. The Arm presentation mentioned above talked about the software development tools like Arm DS connected to emulation and prototyping. Similarly, we co-presented with our partner Green Hills on “Towards Secure and Safe Software Development using Green Hills and Cadence Technology,” showing a demo connecting the Green Hills multi-debugger to virtual platforms, emulation, and prototyping and discussing the use of the Integrity OS on designs running in Palladium. UltraSoC presented on their system-debug capabilities in “Pre- and Post-Silicon Debug and Power Optimization in a 7nm World,” connecting to Cadence emulation, prototyping, and simulation on an automotive demo design, which we cooperated on—you guessed it—in the cloud.

With such a vibrant ecosystem of (1) different processor architectures to run verification on, (2) cloud execution, (3) testing interfaces, (4) models for different processor architectures enabling hybrid emulation (5) test interfaces and (6) software development tools enabling hardware/software co-development, it’s no surprise how productive our users are. We had plenty of new examples CDNLive Silicon Valley. As I had already mentioned, Ampere and AFRL discussed being productive in the cloud. Toshiba Memory gave a great presentation on “System-Level Emulation Performance for Storage Controllers” on how they combined emulation and prototyping, optimized the Palladium execution for speed and then achieved 4.6X speedup by congruently bringing up Protium prototyping. The Tensilica DNA100 verification—presented by the Cadence service team—was, of course, finding itself integrated into actual designs. Last week, at a joint seminar, Arm China showcased their own usage of Palladium emulation in hybrid mode with virtual prototyping and fast models in which they achieved 1000X speed-up over pure emulation (see picture above).

At CDNLive EMEA in Munich, we have more customers talking about their usage of the verification ecosystem—among them, Dream Chip, Intel-Mobileye, Ericsson, Infineon, ST Microelectronics and Texas Instruments—across all verification engines consisting of formal, simulation, emulation, and prototyping.

Exciting times!