Center Stage: The Time For Hybrid Bonding Has Arrived

When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung, or Huawei in your hands.

But while today’s CIS devices currently dominate the use of hybrid bonding, high-performance computing (HPC) is emerging as a new high-growth application for hybrid bonding. This is a result of the trend toward finer pitched interconnects in advanced 3D packaged memory technologies. In addition, the market share of high-end performance packaging, including both 2.5D and 3D packaging, is expected to be $7.87B by 2027, with a compound annual growth rate (CAGR) of 19% from 2021 to 2027, according to Yole Développement. As for 3D stacked packaging alone, it is expected to grow at a CAGR of 58% to 70% during the same period.

Using direct Cu-to-Cu connections instead of bumps and suitable for pitches less than 10μm, hybrid bonding often involves the direct stacking of two wafers, with the space between the two planarized surfaces approaching zero. Hybrid bonding has advantages over conventional micro-bumping, such as enabling smaller dimension I/O terminals and reducing pitch interconnects. But while both hybrid bonding and conventional micro-bumping support higher-density interconnect schemes, hybrid bonding is an expensive process compared to bumping and requires much tighter process control, especially in the areas of defect inspection, planarity measurement, and void detection.

While wafer-to-wafer bonding has already been demonstrated for NAND devices and is currently used in CIS manufacturing for the integration of the imager layer and logic, DRAM manufacturers are also looking to adapt hybrid bonding to replace bumps. Utilizing a hybrid bonding interconnect scheme capable of reducing the overall package thickness by tens and possibly hundreds of microns in certain situations, HBM (high-bandwidth memory) die are vertically stacked in 4,8,12,16 die stacks. The gap between each die is about 30µm when bumps are used, but the gap is nearly zero with hybrid bonding.

It is important to inspect wafers for device yield and interconnect yield; both are needed for a fully yielding device. The bond interconnect must have just the right amount of dishing, a slight recess due to chemical mechanical planarization (CMP), that enables the Cu pad to expand during the bond process. This allows the opposing bond pads to touch while the surrounding silicon remains intact. However, developing a process for controlled dishing across a 300mm wafer is challenging. As a result, tightly controlled electroplating processes are critical. Developing those processes and maintaining them in high-volume manufacturing (HVM) relies on high-precision, high-throughput measurement and control techniques.

Surface defect detection at 0.2µm is the standard for hybrid bonding, as surface defects can create a void as large as 10 times the defect size after the two surfaces have been bonded together. The process to control this is considerably more intensive than traditional back-end quality control in which inspection requires defect sensitivity greater than 5µm. Many of today’s existing back-end inspection tools don’t have the resolution and speed to detect sub-micron defects.

Sub-micron defect sensitivity also adds significant stress to device manufacturers. Traditional back-end processes, such as wafer grinding, wafer-edge trimming, wafer sawing, and taping/de-taping, are considered to be dirty processes that create a significant amount of particles and debris. As such, keeping wafers clean of sub-micron defects is not an easy task in traditional back-end manufacturing.

Hybrid bonding also requires nanometer-resolution quality control and metrology, which is generally unheard of in the back-end process. To ensure reliable Cu-to-Cu surface bonding, a surface recess of less than 20nm is required on Cu pads. The exact recess depth is dependent on the pad size and pitch. This kind of quality control adds an additional burden on device manufacturers.

Fig. 1: Common process defects of hybrid bonding.

And because hybrid bonding is a back-end process involving wafer-edge trimming, wafer grinding and dicing, it demands new inspection standards and metrology requirements during the back-end process, most notably the need for tools with sophisticated image processing and machine-learning algorithms to detect low contrast defects in the active pixel sensor area.

Regardless of these challenges, hybrid bonding is emerging as a star player in the back-end, where today’s needs and challenges are quickly becoming as significant as those the front-end has faced for years.