Challenges In IC And Electronic Systems Verification

Power efficiency, unrealistic schedules, and cost-down considerations are increasingly the top challenges design teams must meet to deliver next generation electronic systems, whether it is for the mobile, server, or automotive market. In addition, a successful chip tapeout does not guarantee the eventual end-product’s success—there are many variables to take into account.

In the first part of this series, we looked at some approaches to address these challenges. A simulation-driven product development process that enables both a top-down and a bottom-up analysis framework was proposed. The top-down planning process helps define higher-level goals or ‘budgets’ for the design of the system, its subsystems and components. The bottom-up process implies each section of the design is individually verified in a virtual prototyping environment with the appropriate level of detail, and the data created from every sub-component enables the simulation of the next higher stage (or subsystem). In this part of the series, we will look in more detail at some of the specific problems that need to be addressed.

Which Problems Should We Solve?
The key technical challenges involved in the design of a system can be categorized as: (a) power budgeting; (b) power and signal integrity; (c) system and component reliability; (d) thermal and mechanical stress, both at the system and component level, and (e) the ability of the system to meet regulatory requirements for electro-magnetic interference (EMI) and electro-magnetic compatibility (EMC).

A modern mobile handset, for example, is no longer just a telephone, and a tablet is no longer just a portable computer (PC). These systems integrate radio frequency (RF), analog, and digital functions in a system-on-chip (SoC) solution with memory, graphics, storage, modems, Bluetooth, WiFi, antenna, LCD, camera, MP3, and broadcast FM support. The industry trend is to deliver rich digital content through wireless connectivity, while seeking to extend battery life. Functions enabled through multiple discrete components are now part of one single SoC.

However, the power consumed by this single SoC must be within a very tight ‘budget’— constrained by the ability of a human hand to comfortably hold a hot surface, and by the size of the battery that can be accommodated in the system (as shown in figure 1 (a). Meeting these challenges requires a comprehensive ultra-low-power methodology that considers power analysis and optimization as key design enablers, from early in the design process through the end. This view is captured best in a comment that Simon Segars, president of ARM Holdings, made in a recent interview, “We need to drive down the energy consumed by the use of electronics. One thing I expect to face is that the generation and consumption of data is going to explode. There’s going to be large amounts of autonomous sensing and those nodes will need sensors, microprocessors, connectivity, and will generate data and send that data to the cloud.”

Figure 1 (a) Power consumption trends vs. battery and thermal limits.

Figure 1 (b) Supply voltage vs. power noise trends.

Power and signal integrity is an increasing problem buffeted by two strong cross-trends. As shown in figure 1(b), the reduction in the power supply levels of a SoC and the increase of power noise (v=Ld di/dt) levels are moving in opposite directions. This trend is expected to worsen as the industry migrates to 3D FinFET technologies, which allow the use of very low supply voltage levels. More dynamic voltage drop induced failures are expected and have been increasingly seen, especially for complex low-power designs with 100+ unique domains, power-/clock-gating, on-chip regulators, etc.

Another area where power noise has a detrimental effect is during chip-to-chip communication. The quality of signal propagation for parallel busses is adversely impacted by signal coupling (signal integrity (SI)) and power noise variations (power integrity (PI)). Accurate prediction of the combined effect of SI and PI noise on jitter requires holistic simulation of the chip’s I/O DDR interface—considering the entire chip I/O bank, including the I/O devices and their associated on-chip power grid, the package and board parasitics (self and mutual), both on the signal and the power/ground traces, and the termination load.

An often-overlooked design challenge that will come to the forefront is reliability, which is critical for 20/16-nanometer (nm) technology nodes. While it always has been known that electromigration and electrostatic discharge (ESD) events can cause integrated circuits (ICs) to fail, the frequency of these events and the likelihood of such failures increases significantly at the advanced manufacturing nodes. Additionally, this effect is compounded at higher temperatures. Addressing this challenge requires comprehensive stress, electro-migration and ESD simulation capabilities.

The impact of elevated temperatures, especially on the silicon, is an increasing concern. If not properly designed, thermal runaways can significantly degrade the performance and Mean-Time-to-Failure (MTF) of a high-performance mobile SoC manufactured in an advanced node (20/16nm). Thermal analysis is a chip-package-system problem. For instance, an accurate thermal picture for the chip can only be created through an iterative power temperature-aware thermal analysis that considers the chip, its package, and ambient conditions.

Most chip or package design teams usually don’t worry about the radiation generated by their chip or system, but this potentially can prevent a successful product shipment. This is especially true for mission-critical applications such as the airbag deployment circuitry in an automobile. Today’s vehicles are essentially large electronic platforms that control all aspects of an automobile’s operation, from safety systems to transmission mechanisms to on-board infotainment systems. However, the ICs controlling these systems are no longer low-frequency, relatively simple designs. They are multi-core, higher-frequency devices with significant amounts of on-chip memories that must be designed in conjunction with the board and cable harnesses to help ensure that near- and far-field spectra meet government regulatory requirements.

Required Changes
As mentioned earlier, if the SoC tapes out on time, it does not automatically mean that a highly integrated and complex system will work fine in the field. So, traditional silo-based single-physics and single-component driven design methodologies must be replaced by a simulation-driven product development process that provides a strategic and inventive approach to consider the inherent multi-physics nature of electronic products. It should enable design team collaboration for shared data and results; allowing extensive design exploration and the use of high-performance and distributed compute environments for rapid turnaround in the critical virtual-prototyping design phase.

In the third part of this series, we will explore ways that a design analysis framework can be achieved.