Chip Design For The Age Of New Mobility

From rapid changes in AI algorithms to ensuring functional safety and reliability, tools tackle automotive chip design challenges.


In the new age of mobility, vehicles are valued more and more for their electronic features instead of mechanical specifications. As a result, companies that are able to own and optimize the design of these critical electronics will capture more of the available profit. This is bringing traditional automotive manufacturers into the electronics business, while simultaneously attracting tech companies like Google and Facebook to the automotive industry.

Electronics will manage all of the most critical functions of an autonomous vehicle. A network of fifty or more LiDAR, radar, camera, and other advanced sensors will detect key features of the vehicle’s environment such as road lines, traffic signs and signals, other vehicles, and pedestrians. After collecting this data, a set of integrated circuits (ICs) will process the gigabits of sensor data being gathered every second and decide on a response.

In today’s vehicles, these ICs are distributed around the vehicle, each managing specific functions. In the future, vehicle architectures will converge, with larger and more powerful domain controller systems-on-chips (SoCs) connected to a centralized processing unit, all implementing artificial intelligence. Current CPUs and GPUs are not equipped to meet the power, performance, and area requirements of a true autonomous vehicle SoC. Chip design companies, carmakers, and tech giants alike are discovering that meeting these requirements will require new silicon and system architectures, developed around artificial intelligence, machine learning, and information processing.

Figure 1: Chip-to-city implications as transportation evolves

So, what are the challenges and how are design tools keeping pace with the needs of the automotive chip market? Let’s begin with design.

Accelerating design cycles
AI entails intense algorithmic computation that will require dedicated hardware to perform at the speeds necessary for automated driving. As companies develop AI hardware, the algorithms will be constantly refined and improved, requiring the hardware team to adapt. The hardware team will need to find a way to modify their design quickly as nascent AI programs change specifications often.

To keep up with rapid change, companies are looking for a proven solution that can increase their productivity and design quality, while accelerating their time-to-market. This explains the increasing interest in high-level synthesis (HLS) for AI logic design. For example, BOSCH Visiontec used HLS to deliver three new image-processing designs in seven months, even though the specifications evolved over the design cycle. And while they were at it, they even improved the design quality.

Alongside the critical AI logic, these SoCs need to interact with the outside world, which is inherently analog. This is where smart sensor systems come into play. The sensor perceives the analog world, and the “smartness” performs some pre-processing before converting the signal to digital, and sending it to the bigger, more powerful domain controller and main processor. At the heart of this interaction is an analog/mixed signal (AMS) SoC that integrates analog and digital circuitry, and sometimes even a micro electro-mechanical system (MEMS), onto a single substrate.

AMS design is challenging due to the multiple design domains at play. To assist in creating these complex SoCs, EDA vendors provide some impressive solutions that integrate analog, digital, mechanical, and other domains that play into creating an AMS SoC. These tools enable designers to produce working proofs-of-concept of all the pieces needed for the smart sensor system quickly, all at a low cost compared to traditional off-the-shelf components and systems design.

Functional safety, verification & design for safety
Once the design is complete, the next step is to verify that all the functionality works as intended. In an automotive application, however, you must go a step further. The automotive industry standard ISO 26262 requires robust testing of the electronic components inside a vehicle for random hardware failures and systematic faults. This testing is mandated with the goal of ensuring functional safety, a critical concern for companies developing automated driving systems.

Ensuring the functional safety of automotive electronics requires a robust toolkit, covering lifecycle management, safety analysis, failure mitigation, and safety verification (Figure 2). This toolkit should include failure modes, effects, and diagnostics analysis (FMEDA) to identify faults and understand the associated risks. Next, a selection of safety mechanisms are needed to mitigate these faults, and verification tools to ensure the design’s safety. Throughout, a lifecycle management solution tracks all tests, results, and design versions ensuring accuracy and compliance with ISO 26262 documentation requirements.

Figure 2: A functional safety flow must include lifecycle management, safety analysis, design for safety, and safety verification solutions.

A functional safety flow is the backbone of automotive SoC verification, but there are two important augmentations to complete the toolset. First, a solution is needed to verify the AMS chips powering the vehicle’s smart sensor systems. New solutions aimed squarely at mixed-signal verification offer fast and accurate analog simulations that integrate nicely with their digital counterparts, greatly speeding up the process.

Second, even with new and innovative tools, hardware simulation alone cannot provide the speed and throughput companies will need to verify their designs and get to market before the competition. Autonomous vehicle SoCs will contain several billion logic gates that must be verified under millions of scenarios. The size of these designs in tandem with the exhaustive verification needed to verify their functional safety stretch simulation past its limits. This is where hardware emulation comes in.

Hardware emulation creates a high-speed version of the hardware design before the actual SoC is created, allowing teams to execute tests at megahertz (MHz) speeds. This is much closer to actual operating speeds for a chip, and much faster than simulation. Emulation also gives software engineers a platform for developing and testing software much earlier in the game. Engineers can even feed the emulation with synthetic sensor input data that will be processed by the virtual SoC in the emulator. Then the output from the emulator can be used in an environment that models the vehicle’s behavior to test how the IP and software respond to stimuli. With emulation, each level of the supply chain will be able to begin development earlier while testing within a model of the entire system.

Preparing for manufacturing & life in the field
Up next is the physical verification of the SoC. This is a big step on the path from a functional design to having a real piece of silicon; in other words, it is where the rubber meets the road. Physical reliability verification ensures that manufacturing of the design will deliver optimal yield, and will operate as intended in the real world.

In the safety-critical automotive world, catching potential reliability issues is a top priority. Issues like electrical overstress (EOS), electrostatic discharge (ESD), and latch-up can cause delayed failures in the field, possibly jeopardizing passenger and pedestrian safety. Advanced reliability verification tools can consider a circuit from both its topology and physical layout in a single analysis environment. The verification team can also import design constraints to pinpoint reliability checks and help identify circuits that are out of compliance.

By now the design has been updated, iterated, verified, and validated in preparation for transferring the design onto actual silicon. But, before any chips leave the fab, the first several hundred SoCs are run through an exhaustive battery of tests to ensure that the chips function as intended. New automotive-grade test technologies target defects at the transistor and gate level. These new methodologies use fault models that specifically target defects internal to each cell. Capturing these otherwise undetectable defects is a must for designers striving to meet the ISO 26262 requirement of zero defective parts per billion (DPPM) in automotive electronics.

Nowadays, SoC test can extend beyond the foundry floor, providing defect detection and diagnosis of individual SoCs over the many years of operation in a car. Built-in self-test (BIST) can test digital logic or memory in the field. Even more exciting are on-chip test controllers that enable a variety of users throughout the supply chain to reconfigure test IP to fit their needs. This even includes over-the-air firmware updates and in-field defect diagnosis and repair.

The success of autonomous vehicles hinges on the ability of a system of advanced sensors and powerful SoCs to perceive and process an immense amount of data in real-time. As a result, these chips will require never-before-seen architectures to meet the power, performance, and area required for autonomous drive. Furthermore, autonomous ICs will need to function with near flawless reliability and accuracy, despite harsh environmental conditions, for years and even decades, much longer than ICs in traditional consumer electronics.

To meet these requirements, innovation is needed throughout the SoC design flow. Fortunately, EDA companies are stepping up with advanced design automation and lifecycle management tools that facilitate collaboration up and down the supply chain to enable the next generation of automotive SoCs.

For more information, download our new whitepaper, IC Design for New Mobility, and listen to the podcast episode, Cars, Mobility, Chip to City Design (and the iPhone 4), below.

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