Chip Industry Technical Paper Roundup: Mar. 10

Thermally aware chiplet placement; DRAM read disturbance; training NN with optical backpropagation; 4D mmWave radar for autonomous driving; fault injection threats at pre-silicon; RowHammer under reduced refresh latency; post-layout optimization for field-coupled nanocomputing.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
DiffChip: Thermally Aware Chip Placement with Automatic Differentiation MIT and IBM
Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies Technical University of Munich
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions ETH Zurich, TOBB, and University of Sharjah
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance ETH Zurich, TOBB, and University of Sharjah
Training neural networks with end-to-end optical backpropagation University of Oxford and Lumai
Road Boundary Detection Using 4D mmWave Radar for Autonomous Driving Stanford University
CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon North Carolina State University

Find more semiconductor research papers here.



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