New paper “Circuit knitting with classical communication, ” from researchers at ETH Zurich and IBM Quantum.
Abstract:
“The scarcity of qubits is a major obstacle to the practical usage of quantum computers in the near future. To circumvent this problem, various circuit knitting techniques have been developed to partition large quantum circuits into subcircuits that fit on smaller devices, at the cost of a simulation overhead. In this work, we study a particular method of circuit knitting based on quasiprobability simulation of nonlocal gates with operations that act locally on the subcircuits. We investigate whether classical communication between these local quantum computers can help. We provide a positive answer by showing that for circuits containing n nonlocal CNOT gates connecting two circuit parts, the simulation overhead can be reduced from O(9n) to O(4n) if one allows for classical information exchange. Similar improvements can be obtained for general Clifford gates and, at least in a restricted form, for other gates such as controlled rotation gates.”
Find the technical paper here and IBM Research writeup here. Submitted April 2022.
Piveteau, C., Sutter D. Circuit knitting with classical communication. arXiv. [Submitted on 29 Apr 2022]
Visit Semiconductor Engineering’s Technical Paper library here and discover many more chip industry academic papers.
Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.
Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Hybrid bonding opens up whole new level of performance in packaging, but it’s not the only improvement.
Why this is becoming a bigger issue, and what can be done to mitigate the effects.
Some 300mm tools are converted to 200mm; equipment prices and chip manufacturing costs are rising.
From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
Manufacturing 3D structures will require atomic-level control of what’s removed and what stays on a wafer.
Disaggregation and the wind-down of Moore’s Law have changed everything.
Leave a Reply