How to minimize design margins with accurate advanced transistor degradation models.
Reliability is a major criterion for integrated circuits (ICs) in safety critical applications, such as automotive, medical, or aviation electronics. A particular effect that contributes to wear-out is device (i.e. transistor) degradation. Its impact on the circuit behavior can be verified by circuit level aging simulations, which are offered by various EDA vendors. However, reasonable results can only be achieved with accurate and efficient device (i.e. transistor) degradation models. This white paper discusses the state of the art and points out opportunities for improvements.
To read more, click here.
Disaggregation and the wind-down of Moore’s Law have changed everything.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Continued expansion in new and existing markets points to massive and sustained growth.
Aging equipment and rising demand are pushing up prices and slowing production.
Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.
Disaggregation and the wind-down of Moore’s Law have changed everything.
It depends on whom you ask, but there are advantages to both.
Research shows significant improvement in time to market and optimization of key metrics.
Efficiency is improving significantly, but the amount of data is growing faster.
Some designs focus on power, while others focus on sustainable performance, cost, or flexibility. But choosing the best option for an application based on benchmarks is becoming more difficult.
The clock network is complex, critical to performance, but often it’s treated as an afterthought. Getting this wrong can ruin your chip.
Moving forward will require a fundamental reconsideration of logic.
After years of research, chipmakers have started combining ultra low-power designs with advancements in harvesting technology.
Leave a Reply