Circuit Reliability Verification For Automotive Electronics

Even non-safety related automotive systems need higher reliability than many other consumer electronics.


By Matthew Hogan and Dina Medhat

In the automotive industry, reliability and high quality are key attributes for electronic automotive systems and controls. Naturally, they are particularly crucial when developing functional safety (FuSa) solutions, where inadequate performance or product failure can lead to injury or death. When it comes to safety-related automotive electronics, ISO 26262 provides a framework for robust and reliable design and verification practices [1]. ISO 26262 compliance is an obligation for competitive products in this market.

But what of the reliability obligations for non-safety related systems? In-vehicle infotainment (IVI) and connected car systems need high reliability integrated circuit (IC) designs for marketability and brand perception. While not FuSa systems (and not subject to the rigors of ISO 26262), these systems also find themselves facing standards compliance that can be much more stringent than the standards normally encountered in the consumer market, such as those provided by the Automotive Electronics Council (AEC) [2]. Out-of-specification performance for these ICs may lead to product recalls and significant negative market reaction, something car manufacturers definitely prefer to avoid.

Understanding how to appropriately apply and comply with these standards and reliability expectations in a competitive marketplace can be challenging. The harsh environment present in automotive electronics operation combined with the high reliability requirements for verification of these ICs provides design and verification challenges that are not commonly encountered when designing and developing ICs intended for less-demanding settings. While questions like which electrostatic discharge (ESD) or electrical overstress (EOS) compliance standards need to be met (and at what level) are often answered in industry standards documents, what is less obvious are the challenges, design trade-offs, and best practices used to achieve compliance with these standards.

Automotive electronics

As more companies expand into the automotive electronics market, a key element to their success is ensuring that designs properly account for the environmental variability associated with automotive use, the stringent quality and reliability requirements with which they must comply, and consumer expectations for performance and reliability. Design teams must understand these conditions and apply the appropriate technology to solve design issues and achieve compliance.

There are a number of factors driving the need for reliability. First, there is the physical environment in which these devices must operate, which includes extreme weather conditions and broad ranges of temperatures. In addition to the climate, other environmental conditions that these devices must endure include ambient heat, vibration, and both extended and start-stop operation. Designing to meet this expansive set of requirements is typically a new experience for many IC design companies, particularly those that were previously focused on consumer electronics.

Another reliability requirement that is new to many designers is the expected lifespan for these designs.  While consumer products typically operate for a few years, an automotive device is usually expected to last at least 10-15 years, even extending to 30 years for some applications. In addition, an automobile creates its own system, with a significant amount of connectivity between devices that compounds the criticality of device reliability. In many cases, if one device fails, and redundant systems are not employees, the entire system may be compromised. This forces designers to consider a new host of “failure over time” design stresses, such as time-dependent dielectric breakdown (TDDB), and learn how to analyze and account for these effects. The expected product life also puts a strain on new technologies that do not yet have an in-service longevity track record.

Automotive IC reliability verification

Designers have the responsibility of ensuring that their designs are reliable by verifying electrical performance before tapeout.  The AEC electrical component qualification requirements identify wearout reliability tests, which specify the testing of several failure mechanisms:

  • Electromigration
  • Time-dependent dielectric breakdown (or gate oxide integrity test)—for all MOS technologies
  • Hot carrier injection—for all MOS technologies below 1 micron
  • Negative bias temperature instability
  • Stress migration

Design verification against these failure factors ensures that the actual device electrical performance will meet reliability expectations. However, traditional IC verification flows leveraging design rule checking DRC), layout vs. schematic (LVS), and electrical rule checking (ERC) techniques may have trouble validating these requirements, because these tools each focus on one specific aspect of design verification. For example, automotive applications typically face high operating voltages and high electric fields between nets that can lead to oxide breakdown. Electrical fields can influence sensitive areas on the chip because high-power areas (60V, 80V, 100V) are commonly located next to logic areas (1.3, 1.8V, 5V). Consequently, when designing and verifying many smart power processes, designers must deal with metal spacing design rules that are dependent on voltage drop. Typical design constraints might look like these:

  • Metal2 minimum spacing can be x if voltage drop across lines is up to 30V, and it will be y if voltage drop across lines is up to 80V. Where y > x, similar rules apply for the rest of the metal layers.
  • Minimum spacing between metal and poly is x where voltage difference is higher than V
  • Shapes on a specified metal layer can’t cross a specified area, based on the voltage difference.
  • It is not allowed to cross an adjacent metal level if voltage drop is higher than V

Trying to implement such rules in the entire design flow starting from layout routing implementation through DRC is too conservative, as well as inefficient, due to lack of voltage information on nets (both in schematic and layout). Trying to achieve this goal with traditional exhaustive dynamic simulation is simply not practical, due to the turnaround time involved, and, if the design is very large, it may not even be possible to simulate in its entirety. Design teams need a way to determine the voltages at all internal nodes statically.

Electronic design automation (EDA) solutions that provide advanced reliability verification can quickly and accurately evaluate customized electrical requirements. These tools provide unified access to all the types of design data (physical, logical, electrical) in a single environment to enable the evaluation of topological constraints within the context of physical requirements. Let’s look at some examples, using the Calibre PERC reliability verification platform from Siemens EDA, a part of Siemens Digital Industries Software, as an example of this advanced reliability verification automation.

Voltage-aware design rule checking

Calibre PERC provides a voltage propagation functionality that can help perform voltage-dependent layout checks very efficiently while also delivering rapid turnaround, even on full-chip designs. Figure 1 depicts the automated flow for applying voltage-aware design rule checking (VA-DRC), using a DRC sign-off deck from the foundry. The flow starts by identifying and defining the supply voltages for the design, then using the voltage propagation functionality to propagate supply voltages to internal design nodes (based on rules for the propagation criteria for every device type). DRC rules incorporated into the Calibre PERC logic-driven layout (LDL) functionality [3,4] perform the DRC checks directly, or use the Calibre PERC tool to generate text markers to be used later with the DRC sign-off decks. Errors can be debugged with a results viewing environment, such as the Calibre RVE interface. This debugging environment helps designers debug results from the topological perspective for voltages propagated to internal nets, as well as from the geometrical perspective.

Fig. 1: An automated flow for applying VD-DRC checking to a design.

Looking at a specific rule example:

Metal2 polygon spacing between two nets should be >= 0.5 um
if the voltage difference between these two nets is greater than 40V

Figure 2 illustrates the end result, a portion of the design where violations of this rule are highlighted (red arrows).

Fig. 2: Rule check violations.

Spotting these violations requires several steps:

  1. Define the supply voltages for this design.
  2. Propagate the supply voltages through devices to the internal nodes, which results in attributes for the minimum and maximum voltage that every net can see. These attributes are reported as ranges for the internal nets.
  3. Annotate these ranges to the polygons of these internal nets.

Figure 3 demonstrates how the results are reported from the topological perspective in the debug environment. As shown in the results, nets “OUT2” and “OUTA” are from different voltage domains, where the difference between the maximum voltages propagated to these nodes is (50V – 5V = 45V). This difference is greater than the 40V that the rule checks for. Therefore, the spacing for metal2 polygons between these two nets must be verified against the 0.5 um constraint.

Fig. 3: Portion of the topological results identifying conditions requiring additional checking.

In addition to debugging the voltages from the topological perspective, the user can also debug the results from the geometrical perspective using a results viewer. Figure 4 illustrates that there are two violations for our rule, where the spacing was 0.25 um & 0.3 um. These violations are the ones highlighted in figure 2.

Fig. 4: Portion of the geometrical results showing the two violations.

Negative voltage checking and reverse current

There is another important reliability concern in the automotive area—how to handle negative voltages that occur in automotive applications—that is closely tied to the processing of reverse current issues in high-voltage electrical rule checking.

This type of checking has two sides: schematic and layout. We’ll begin with the schematic side. Designers must specify which ports on the schematic are subjected to negative voltage. They can then use the voltage propagation functionality to propagate these negative voltages across devices, based on user-defined propagation criteria for the different device types. Propagating the negative voltages helps designers identify all the nets in that design that may become negative, based on the Calibre PERC static approach.

The propagation criteria may include a voltage drop definition to be taken into consideration while propagating through the devices, which is also supported by the voltage propagation functionality. Including this criteria leads to the negative voltages decreasing in absolute value when they are propagated through devices. The propagation should be terminated if the internal net has positive voltage. The designer can now identify all devices attached to these nets that have propagated negative voltage.

The Calibre PERC functionality can perform a cross-reference between the schematic and the layout to capture the injectors’ locations on the layout. Now, moving to the layout, designers can run the needed geometrical operations, using tools like the Calibre nmDRC platform or Calibre PERC LDL DRC, with the violations from both schematic and layout side being debugged using a results viewer, so the designer can highlight the results and analyze them.

Using Calibre PERC and Calibre nmDRC technology together provides designers with an easy, automated, and efficient flow to perform checking for both negative voltages and reverse current issues in automotive applications. From a concept perspective, this automated flow is similar to what was shown in figure 1.

ESD and latch-up checking

There are other circuit reliability concerns that are important for automotive applications, such as electrostatic discharge (ESD) and (voltage-aware) latch-up checking, and there are many design rules for these issues that address both schematic checking and layout checking [5,6]. For schematic checking, the rules are directed more towards verifying the presence of the appropriate protection schemes from a topological perspective. Users can perform checks on circuitry directly connected to pads, as well as checks on the ESD network. For layout checking, the rules focus on verifying the point-to-point parasitic resistance between the pad and the ESD device, checking current density between pad and the ESD device, detecting PMOS/NMOS devices sharing the same well, detecting PMOS/NMOS field oxide parasitics, detecting latch-up issues, and more. All these types of verification can be addressed with an advanced circuit reliability verification tool.


There is no doubt that electronics are impacting the automotive market, and this trend is expected to continue increasing. As companies move into the market to take advantage of the opportunities they see, they will need to understand how layout variabilities affect design quality and reliability requirements. Foundries often provide reliability rule decks that establish a baseline for reliability verification needs for a given process node, while EDA providers supply the tools that present this data to designers in an easy-to-use automated system.

Circuit reliability verification for automotive applications is a challenging task, which only increases as the technology advances. Advanced circuit reliability verification tools such as Calibre PERC include specific technologies to make efficient, automated circuit reliability verification practical, helping designers achieve the reliable, accurate, and comprehensive verification necessary to ensure a robust and reliable design.

As the final piece of the ecosystem, automotive IC designers must understand both the requirements and the solutions to ensure their designs meet the stringent electronic reliability requirements while remaining profitable to manufacture.

For more information about automotive reliability verification and the Calibre PERC reliability platform, download copies of our white papers:


  1. “Road vehicles – Functional safety”, ISO 26262-1:2018,, 2021.
  2. Automotive Electronics Council, “AEC Documents,”
  3. P. Gibson, F. Pikus, L. Ziyang, S. Srinivasan, “A Framework for Logic-Aware Layout Analysis,” Quality Electronic Design, (ISQED), 2010, 11th International Symposium on, pp. 171-175, 22-24 March 2010, doi:10.1109/ISQED.2010.5450415
  4. K. Kollu, T. Jackson, F. Kharas and A. Adke, “Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug,” 2012 IEEE International Conference on IC Design & Technology, 2012, pp. 1-5, doi:10.1109/ICICDT.2012.6232874.
  5. M. Muhammad et al., “An ESD design automation framework and tool flow for nano-scale CMOS technologies,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, 2010, pp. 1-6.
  6. E. Gevinti, M. Fragnoli, L. Cerati, A. Bogani and A. Andreini, “HBM ESD EDA check method applied to complete smart power IC’s — Functional initialization and implementation,” 2013 35th Electrical Overstress/Electrostatic Discharge Symposium, 2013, pp. 1-10.

Dina Medhat is a senior technologist for Calibre Design Solutions at Siemens EDA, a part of Siemens Digital Industries Software. She has held a variety of product and technical marketing roles in Siemens EDA. Medhat received her BS and MS degrees from and is currently engaged in PhD research at Ain Shams University in Cairo, Egypt.

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