How to deal with internal routing congestion at N5.
Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route
(PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dimensions. We present morphological results of the patterning scheme and discuss the impact of process variations on SV resistance obtained from empirical resistance simulations.
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