Challenges in today’s tightly-packed designs cannot be solved by deploying physical verification techniques in isolation.
Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly become a critical and essential technology that addresses the increasing complexity of geometrical checks used in both established and emerging integrated circuit (IC) technologies. Traditional electronic design automation (EDA) verification tools handle either the physical verification of the layout shapes or the electrical verification of the circuits, but not both [1].
For as long as there have been design rules, there have been design rule checks, and for as long as there have been netlists, there has been electrical verification, but these were historically distinct and separate verification flows. However, designers are facing new verification challenges in today’s tightly-packed designs that cannot be solved by either of these verification techniques in isolation.
Context-aware checks combine the physical layout of a component with its electrical implementation and analyze that information in tandem to evaluate a wide range of design conditions, from advanced design rule compliance to circuit and reliability verification to design optimization and finishing.
One use of context-aware PV is the optimization of metal fill insertion. Metal fill is a critical step at advanced nodes to ensure high yield and manufacturability. However, inserting metal fill adds capacitance, which affects timing, especially for critical nets in the design. As radio frequency (RF) and analog designs are highly sensitive to parasitic capacitive coupling between signals and fill, there is a need to identify critical design elements (nets/devices) in these designs so they can be treated differently when adding fill to a layout. However, manual identification of these elements is time-consuming and prone to human error. For a fast, accurate and efficient process, designers need a methodology that can automatically link design awareness with metal fill insertion.
Designers define critical nets by their name, or their connectivity to certain device types or circuit structures. To accurately capture these critical nets for an automated fill flow, these criteria must be coded into a circuit reliability verification tool such as the Calibre PERC reliability platform [2] from Siemens EDA.
From the designer’s perspective, two critical factors in efficient reliability verification are:
That second factor (automated pattern recognition) is particularly useful for designers who need to find and analyze specific design patterns of interest quickly and efficiently. For ease of use, as well as broad applicability, designers need both the flexibility to define these patterns in a simple way (e.g., SPICE) that is independent of the design cell names, and the ability to define some margin around a design pattern, so that similar, but not exact, matches can be identified for analysis when appropriate [3].
As demonstrated in figure 1, designers only need to:
Using this SPICE pattern template functionality allows design teams to easily add or remove circuit schemes to the template, based on the methodology applied by the company for critical patterns or critical nets connected to certain patterns.
Fig. 1: Circuit recognition using SPICE pattern templates to identify critical design nets/devices.
The designer’s ultimate goal is to maximize the fill insertion ratio while minimizing the resistance and capacitance (RC) impact of fill on critical nets. Once designers can automate the identification of critical/sensitive nets and devices, the next step is to automatically provide enhanced protection during fill insertion.
However, identification of critical/sensitive nets and devices requires a design layout netlist, which is output from a layout versus schematic (LVS) run. The very large designs common in recent technology nodes typically require very long runtimes for LVS runs, which slows down the process considerably. The Calibre PERC flow can re-use information from a previous LVS run database, eliminating the need to re-extract the layout, minimizing schedule impacts.
The Calibre PERC software then uses its context-aware functionality in combination with the designer-defined criteria (net name or connectivity to certain device types or circuit structures) to identify critical nets in the design layout netlist, find the corresponding geometries in the design layout, and generate geometrical marker layers for these critical nets in GDS/OASIS format [4,5]. Designers can then merge the markers GDS/OASIS with the design GDS/OASIS to capture target design nets that overlap for special spacing constraints consideration during fill shape generation. Next, they use a metal insertion EDA tool such as the Calibre YieldEnhancer tool with SmartFill technology to insert optimized fill [6], and simulate the design with the optimized fill shapes insertion to check performance. Figure 2 demonstrates this methodology.
Fig. 2: Methodology for linking design awareness with metal fill insertion.
Context-aware verification flows were developed to solve demanding design and manufacturing challenges in both established and emerging nodes. Automated context-aware checks have been achieved by leveraging new EDA tool capabilities and advanced integrations across multiple verification domains. A prime example of context-aware verification is the ability to link design awareness with metal fill insertion. The methodology provides significant benefit on high-speed intellectual property (IP) designs by minimizing the parasitic capacitance increase due to fill patterns. Re-use of the LVS run database reduces design turnaround time, while circuit pattern recognition helps designers automatically capture complex topologies to identify critical nets in the design. Linking context-aware topology analysis with fill optimization ensures designs will meet both their performance and manufacturing targets.
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