Controlling The Reliability Of Silicon Carbide-Based Devices

The development of wide bandgap silicon carbide (SiC) compound semiconductors has proved to be extremely beneficial for power conversion applications. Capable of switching at significantly higher frequencies, and with higher breakdown voltage characteristics, SiC power transistors are quickly becoming an attractive silicon alternative for high power density and/or high-efficiency power conversion applications. However, despite the material’s characteristics and many similarities to silicon, there are several notable differences. During SiC process fabrication, many of the methods used to test and validate a silicon device can be transferred across, saving time and budget. The differences between the materials and the conditions under which they operate have highlighted the need for additional and an alternative approach to long-term reliability testing.

Material differences between Si and SiC require additional testing

During the development and release process of our CoolSiC series of devices, we researched to determine the critical failure mechanisms that would impact the long-term reliability of these semiconductors. Only in this way safe and reliable operation of the SiC-based portfolio of devices can be ensured.

From the research, the following aspects of SiC necessitated a different approach to qualification testing:

• The differences between Si and SiC materials and the impact of specific SiC defect structures, anisotropies, and other mechanical and thermal characteristics
• The impact of significantly higher electrical fields both within the material itself and external interfaces
• The consequences of combined operation at high voltages (Vds > 1000 V) and fast switching transients (> 50 V/ns)
• The implications of using a wide bandgap material in MOS-based devices

Analysis of the above led us to establish new tests for SiC power devices to take into account of the different operating conditions that SiC devices encounter compared to their silicon counterparts. These include emphasizing a mission profile stress analysis approach to device characterization and validation.

SiC MOSFET reliability improvements through stress testing

During the early stages of commercialization, the reliability of SiC MOSFET devices did not achieve that of their silicon equivalents. The reason were mostly weak spots in the gate oxide layer resulting from distortions, termed extrinsic defects and being described by local material thinning. A thicker gate-oxide layer and screening using a high voltage pulse technique resulted in a reduction of the gate-oxide defect rate of the final products. However, the consequence of a thicker gate-oxide layer slightly increases the device on-resistance.

Infineon developed two stress tests to evaluate the impact of extrinsic defects on gate-oxide reliability, both to place devices under stresses they might be expected to operate under in real-world conditions. The first of these is a marathon stress test which serves to assess the behavior of the actual technology during the development phase, and the second, a gate voltage step-stress test, is used to gather a quick information in form of benchmark between different technologies resp. vendors.

Marathon stress testing

Because extrinsic failures are relatively rare, the developed marathon stress test involves testing of thousands of SiC devices in parallel with operating conditions closely matched to real-world requirements. Test cycles are typically at least 100 days to achieve sufficient extrinsic failures on a realistic test sample size. To physically manage a test of such a large number of devices in a furnace, the team constructed a single package comprising multiple devices, so that multiple packages could be placed on a test board. Even though large sample sizes are required, the marathon stress test is an excellent way of predicting lifetime failure rates of SiC MOSFETs during normal operation. It is the baseline for FIT rate calculations since it delivers important acceleration model parameters.

Gate voltage step-stress test

A faster way of estimating the gate oxide stability of MOS device is through a gate-voltage step-stress test. Using a significantly smaller sample size, typically 100 devices, this test involves testing at the maximum permitted junction temperature for a defined stress period of, say 24 hours. In that period the gate voltage is increased stepwise by 2 V starting from the recommended gate voltage for turn on. After each bias step, failed devices are counted and removed. The test will be continued until all devices show hard fails. The failure distribution can be displayed by using a so-called Weibull plot. The gate voltage step-stress test is an ideal way to provide a qualitative comparison of the gate-oxide reliability of devices from a variety of different manufacturers.