A Delicate Balancing Act

The end of CMOS is in sight yet again, but this time there seem to be far fewer options.

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ver since the patent for complementary metal oxide semiconductors was awarded to Frank Wanlass at Fairchild in 1967, CMOS has proved to be one of the most durable technologies in electronics history. It has powered devices worth trillions of dollars in sales, been the recipient of an estimated $600 billion in R&D, and become the basis of some of the most refined manufacturing processes in history.

But all good things must come to an end, and that’s causing great consternation in some circles. At 20nm and beyond, bulk CMOS is still useful for some applications such as processors and memory chips. It is not so useful, however, for many SoCs, particularly at those advanced nodes. There is entirely too much variability in the process, and defect density will continue to rise at each new node to the point where it will become even less useful.

There have been predictions about the death of CMOS for the better part of the decade. With stress, lithography advances and even some interesting work in 3D stacking, CMOS may yet be extended a generation or two on the Moore’s Law road map. But the technology is getting to the point where overcoming its limitations is becoming problematic.

IBM and AMD moved to silicon-on-insulator several nodes ago, and there is work in a variety of other materials ranging from silicon germanium to gallium nitride. At the far end of the spectrum, there also have been major advances in carbon-based devices such as nanotubes, nanorings and graphene. While these new technologies offer some benefits, the ability to manufacture them with consistency and en masse has a long way to go.

The problem is that as we push down each new node from 28nm, something has to give. Either those new materials have to be commercialized with a consistent manufacturing process, or new materials have to be introduced into existing processes that have been perfected over four decades. The challenge is figuring out what to keep, what to replace, and how to do that with the least disruption.

But that challenge also needs to be answered pretty quickly. It will still be possible to create processors and memory chips down to 11nm on CMOS or SOI technology. For the fabless SoC and FPGA developers, however, it may be a lot more time-consuming and more expensive to create reliable chips. Perhaps even worse, in the past there were large chipmakers leading the charge and pouring huge sums into R&D. Today there are lots of smaller fabless companies that don’t have the clout to organize an entire industry.

As an industry, we’ve been cruising along waiting for some really smart people to find a solution to a pesky problem. Unfortunately, we may be reaching the point where we have to think of some completely new alternatives, and that will require a delicate balance between keeping what we can and investing in a whole new approach.

–Ed Sperling