Double Patterning: Challenges And Possible Solutions In Parasitics Extraction

The most promising solutions to 20nm litho challenges may come from some not-so-obvious places.


By Dusan Petranovic and David Abercrombie
Double patterning (DP), as the simplest form of multi-patterning techniques, is receiving lots of attention right now. The need for double patterning techniques is driven by the physical limits of the dimensions that can be resolved with current light sources and lenses, as well as by the difficulties and delays in deploying next-generation lithography techniques. It is expected that double patterning and multi-patterning will be used broadly in the industry at 20nm and smaller technology nodes if the current manufacturing issues of EUV are not addressed in time.

Litho-Etch-Litho-Etch (LELE) is the most common technique of double patterning used in 20nm technology. The LELE DP technique first separates dense layouts that cannot be printed with a single exposure into two lower-density layout masks. It then uses two separate exposure processes to form two coarser patterns, which are then combined/superimposed to form a single finer image on the actual wafer. Figure 1 illustrates a 20nm layout that could not be printed with a single exposure (Fig.1a), but was successfully printed by splitting the layout into two masks.


Figure 1. After an unsuccessful single exposure (1a), this 20nm layout was split into two masks (pink and yellow) to produce an acceptable final silicon image (1b).

The adoption of LELE DP processing affects many aspects of the design flow, including parasitics extraction and the signoff methodology. The unavoidable misalignment of the layout masks causes variations in coupling capacitances between the polygons that are on different masks, which in turn affects both the couplings and the total capacitances of the nets.

As shown in Figure 2, some segments that are on different masks get closer together, while other segments get further away from each other, all due to relative mask shift. These shifts increase and decrease the coupling capacitances respectively. Total capacitance also is affected, due to asymmetry in the layouts. Capacitance change impacts circuit performance (the crosstalk, delay, or other circuit parameters), and must be accounted for in-circuit analysis.


Figure 2. Changes in the distance between figures caused by manufacturing variation affect both coupling capacitance and total capacitance.

Errors introduced by DP depend on mask displacement amount. Impact on coupling capacitance can be large, even while it is smaller on total capacitance, due to the different impact on coupling capacitances at the opposite sides of the conductor segments. Figure 3 shows the impact of an 8nm mask misalignment on total capacitance (left) and coupling capacitances (right) of a 20nm design. Vertical axes represent the number of the capacitance components, while horizontal axes show the percentage error relative to a non-shifted mask case. Standard deviation in total capacitance case is 6.4%, while it is much larger for coupling capacitance (23.3%). It should be noted that an 8nm misalignment is larger than a consensus estimate, and was used to provide a worst-case example. Also, the mask overlay impact on circuit parasitics, and consequently circuit design parameters, is design-dependent.


Figure 3. Error (by percentage), relative to non-shifted masks, introduced to total capacitance and coupling capacitance by a mask overlay of 8nm.

For a 6nm displacement, an error of about 17% on coupling and 6.5% on total capacitances was observed using typical test structures for evaluation. The error for a 2nm shift is, as expected, much smaller, in the range of 5% for coupling capacitances and about 2% for total capacitance.

Extraction approaches
The foundries and the EDA companies are striving to estimate the electrical impact of double patterning, and to develop extraction techniques that effectively and accurately analyze these DP effects. The dilemma is the tradeoff between simplicity (extraction methodology and analysis flow) and accuracy (analysis of the impact of DP on the performance parameters). The approaches, accordingly, can be classified into extraction-based techniques and analysis-based techniques. In extraction-based techniques, the goal is preservation of the existing extraction and analysis flow by using the common corners-based extraction approach, while the analysis-based technique shifts the burden to the analysis phase by extracting the netlists with sensitivities to spacing between the polygons, then applying statistical analysis techniques.

It also must be noted that either colorless or colored layouts [1] can be used in the extraction process. Colored layouts enable less conservative extraction, resulting in improved performance of the designed circuit. Although layout coloring can be performed with EDA tools or scripts provided by foundries, not all foundries like the idea of designers coloring the layout, and methodologies to extract the parasitics based on the original non-colored layout are needed. In the case when full coloring by customers is not supported, some flexibility is provided to customers, in the sense that they can put markers (or anchors) on the polygons to determine the mask on which those polygons should be placed.

Extraction-based techniques
Extraction techniques developed at Mentor Graphics to handle the impact of double patterning are summarized in Figure 4.


Figure 4. Extraction techniques.

The simplest technique to quickly analyze the impact of DP on circuit performance is to scale the capacitances and resistances by an estimated fixed value. This technique was used at the very early stages of development, but is not accurate enough for any real chip analysis.

The technique currently used by all major foundries is based on the dielectric constant change. The foundries provide tables for the dielectric constant change as a function of polygon width and spacing to other polygons. The dielectric constant change should produce the same effect on coupling capacitance as would the decrease or increase of polygon spacing due to maximum mask misalignment. As a consequence, two new corners (DP max and DP min) are produced for each original foundry corner, resulting in a total of 15 corners for a typical five foundry corners variation handling approach.

However, this approach is too conservative, because it accounts for unrealistic cases in which both left and right neighbors of a given polygon move towards it or away from it at the same time. In addition, it is typically applied to colorless layouts, which also introduces conservatism, since the same dielectric constant change is applied to the same mask polygons, even though they do not shift relative to each other. To alleviate this issue, anchoring is introduced as a way to specify which polygons belong to the same mask, to ensure that the dielectric constant change is not applied to the pairs of polygons located on the same mask.
An alternative, less conservative, and more physical approach has been proposed by Mentor Graphics. In this approach, in addition to regular foundry corners, custom corners are used to account for the impact of spacing change between the polygons caused by mask misalignment. Unlike the dielectric constant change-based approach, the custom corner approach does not consider unrealistic cases, but rather, accounts for any desired number of actual/possible mask shifts. In this way, the coupling capacitance on one side of a polygon that is surrounded by polygons belonging to a different mask increases, but at the same time, it decreases on the other side of the polygon. This approach will be applied to colored layouts, further improving the accuracy of the extracted capacitance and estimation of DP impact on circuit design parameters.

Both of the above extraction-based approaches introduce additional corners to the original foundry corners, which increases both the conservatism in extraction and simulation time. The foundries are doing analysis in an attempt to reduce the number of additional DP-related corners, since not all the original foundry corners require two additional DP corners to account for the worst case DP effect. A reduction to 11 corners has been reported, but it is not certain how well the corners cover the variation space. A single netlist is typically generated for each corner, and an increased number of netlists has a significant impact on both the simulation time and the overall analysis effort. To reduce the number of netlists, clustering of corners can be performed and a single multi-valued netlist produced for each cluster, thus reducing the number of netlists.

The most accurate DP extraction technique requires a completely different approach, which we will call the simulation-based approach. A netlist with sensitivities to spacing is produced, and a statistical method (e.g., Monte Carlo Analysis for analog designs, or Statistical Static Timing Analysis for digital designs) is used to obtain the distribution of the design parameter(s) due to DP. Accuracy is achieved at the expense of introducing statistical analysis, and it is questionable as to how it would be received by the designers.

1 David Abercrombie. “Colorblind—Colorless versus Two-Color Double Patterning Design,” Semiconductor Manufacturing & Design, March 2012.
Some of the material for this article was derived from “Double Patterning: Challenges and Possible Solutions in Extraction and Signoff Methodology,” Dusan Petranovic, Jim Falbo, Nur-Kurt Karsilayan: TAU 2012, Taipei, Taiwan, January 2012.


—Dusan Petranovic is the interconnect modeling technologist in the Design-to-Silicon Division of Mentor Graphics. David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.