Meeting market demand with higher precision at lower costs.
Not all chips are created equal, and this is viewed as both a blessing and a curse by semiconductor makers. On one hand, chips can be screened for certain attributes, and some of the chips can be sold for higher prices than others. On the other hand, variations in the production process cause silicon performance to greatly differ, leaving chip makers with a wide and somewhat unpredictable distribution of material.
Some chips may perform better than others, while others consume less current than their counterparts. Sometimes certain chips generate less internal noise than most, and others might run at a higher speed. Semiconductor vendors take advantage of this situation, screening chips so that they can sell the same design at different product specs to different markets.
Manufacturers test the chips for attributes that match specific needs of various end markets and classify them into Bins, usually based on power and frequency. Binning tailors the chip population to different price and performance points and is intended to take advantage of all the material that was produced, especially since the design adhered to the ‘plan-for the-worst-case’ methodology.
Binning may add to the complexity of operations, by adding SKUs to manage, but that’s always worthwhile. If it weren’t, then the specification would simply be written to the extreme element and every part would meet that specification.
It is required especially in high performance chips where the potential financial gains (or risks) are big. Binning not only allows manufacturers to maximize chip performance and serve multiple markets, it can also help ‘relax’ guard-bands and reduce area and power. Designing according to bin demands allows chip makers to improve die size, power and parametric yields.
Some chip types are binned by speed. Some are sorted for other criteria like operating temperature and voltage, output drive current, leakage, and so forth. Microprocessors (MPUs), for example, are binned for high or low clock frequencies. Such tests are normally performed by sophisticated test equipment on chips after they have been packaged, at Final Test.
Many tests are either too difficult to perform at wafer sort, or the cost to perform them at this stage is prohibitive. Speed testing is one of these.
Chip makers could potentially reduce costs if they would be able to test for speed at wafer sort so that they didn’t have to package all of the parts before learning how fast they were. It is especially crucial with the rapid adoption of innovative but costly heterogeneous packaging techniques. Scrapping or shelving an assembled 2.5D package because it did not meet the required spec is a dread every manufacturer fears all too well.
But today’s best-known methods don’t support speed testing at wafer sort. Standard wafer probe cards have very long signal leads and cannot support very high current demands, so speed testing at such as early stage requires very costly custom probe cards.
For some chips, binning needs to be very precise, and that precision often means that a more sophisticated tester, one with higher resolution, must be used to perform the test, driving up test costs.
What if there was a way to know exactly how fast a chip would perform before having to conduct a speed test? What if alternatives for these tests could be performed at wafer sort?
Even more, what if all binning, no matter how precise, could be done at wafer sort?
In fact, it can. Early and fine binning can now be achieved thanks to new data sources providing visibility at much earlier stages in production.
proteanTecs enables manufacturers to bin chips virtually, in a straightforward and inexpensive way based on Deep Data. By using a combination of tiny on-chip test circuits called “Agents” and sophisticated AI software, chip makers can find relationships between any chip’s internal behavior and the parameters measured during the standard characterization process. Those relationships can be used to measure similar chips’ internal characteristics at wafer sort to precisely predict how chips would perform during Final Test, even before the wafer is scribed.
This is much more than simple pass/fail testing that is normally performed at wafer sort. Instead, by using proteanTecs’ analytics platform, Proteus, chips can now be sorted into precise operating categories to achieve very fine binning even at this early stage.
The figure below shows a binning dashboard in the Proteus analytics platform:
And the plot below outlines visibility of VDDmin bin thresholds across multiple lots:
The blue dots represent chips that have VDDmin levels that meet the required product specification and will be binned in the target bin. The orange dots represent chips that require higher VDD levels and will be binned in a high-power bin. These bins are based on predicted VDDmin estimations derived during wafer sort, as opposed to existing best-known binning methods in which costly tests are run to determine VDDmin only at Final Test.
In this way the chip maker can know almost exactly how the wafer’s packaged parts will be binned before a single chip is packaged. They can pick and choose which wafers to scribe, singulate, and package and which wafers to put aside for later. They can even decide, one by one, which of a wafer’s chips to package, and which might be discarded or saved in a die bank for later use.
At proteanTecs we sometimes call this early binning “Shift Left Binning,” because the entire binning process is done much earlier in the manufacturing process to provide simpler inventory control and reduce wasted packaging efforts to improve the cost of goods sold (COGS). Think of the risk that can be avoided when a single 2.5D package can run a price of nearly $1,000.
To see how this might be used, let’s consider a manufacturer who uses Proteus and finds that a certain wafer will only yield slower parts. They can put that wafer aside if there is a stronger market for the faster version of the same parts. Wafers that promise to provide a higher percentage of fast parts can then be prioritized for package and test.
Early and fine binning can index individual chips on a single wafer to very narrow operating ranges. This can be used to benefit more recent MPUs that use multichip module (MCM) or 2.5D packaging techniques to intimately connect speed-screened processors and memory for a speed advantage. The operating parameters of the chips used in these products must be carefully matched prior to being packaged. With today’s best-known methods (called “KGD” for known-good die) this involves costly speed testing at wafer sort. With the Proteus platform such speed matching can be performed without actually having to run a speed test, since the Agents will indicate which chips will run at which speed without requiring an actual speed test.
Shift-left binning also plays a vital role in reliability screening. To ensure quality levels of finished goods shipped to customers, routine tests are performed to weed out defects. Even after extensive testing has been performed, some of the deployed parts will still eventually fail under certain applications and environmental conditions or after running for some time. These have what are considered ‘reliability defects’ which are latent, i.e. not apparent during the production stages.
Accelerated lifetime tests, such as burn-in, are performed to simulate operation of the IC under extreme voltage and temperature conditions. Chip makers use these to artificially ‘age’ the IC and screen out reliability defects before the product is deployed to its eventual mission. Just as with performance binning, these tests are performed on packaged material, adding yet to overall production risks. During test, the product’s expected lifetime is also determined so manufacturers can bin according to reliability grading.
Proteus provides a way of classifying the dies into bins with varying degrees of reliability at an early stage, enabling predictions about reliability behavior of different classes of die, already at wafer sort. Not only does the process provide significant savings, but supply can be tailored to meet market demand for various applications according to reliability requirements.
Yet another benefit of shift-left binning comes from the migration of more complex chips away from monolithic designs to designs that use multiple chiplets, each of which might perform half of the end product’s functions. Two or more chiplets are packaged together and operate as a larger single-chip device. This approach is already popular with FPGA vendors, and is gaining traction in higher-end MPUs. These chiplets must be speed-matched to each other before they are packaged together, a task that Proteus can perform much more cost-effectively than can currently-established methods.
Binning at wafer sort has been a dream for manufacturers for a long time but it has either been too costly or too difficult to perform in most situations. Today there is a new method, through Deep Data analytics, to perform binning at wafer sort while increasing the resolution of the bins.
This brings several benefits to chip manufacturers since unusable material need not be packaged. Not only will this reduce the cost of goods sold (COGS), but it improves inventory turns, since it shrinks finished goods inventory (FGI) and it allows the manufacturer to better match its inventory to the market’s requirements. Chips that aren’t immediately required can be kept aside in wafer form or in a die bank, waiting for the right market to develop before being packaged.
It’s a simple solution which provides net cost savings direly needed by an industry undergoing scale.
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