Silicon photonics uses existing CMOS manufacturing infrastructure and techniques but lacks mature models that take into account known CMOS process variations and their effect on photonic component behavior.
Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS process variations and their effect on photonic component behavior.
In this paper, the authors study the effect of a well-known random process variation, line edge roughness (LER), present in the lithography and etch process, on the performance of a fundamental silicon photonics component (the Y-branch) through virtual fabrication simulations. Ensemble statistical virtual fabrication and FDTD photonic simulations across a range of LER amplitude and correlation lengths are reported. These results indicate that component performance can be adversely impacted by random variations in the lithography and etch processes, depending on the statistical nature of the LER perturbations.
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